60-dB SNDR 100-MS/s SAR ADCs with threshold reconfigurable reference error calibration CH Chan, Y Zhu, C Li, WH Zhang, IM Ho, L Wei, U Seng-Pan, RP Martins IEEE Journal of Solid-State Circuits 52 (10), 2576-2588, 2017 | 51 | 2017 |
A 312 ps response‐time LDO with enhanced super source follower in 28 nm CMOS Y Lu, C Li, Y Zhu, M Huang, SP U, RP Martins Electronics Letters 52 (16), 1368-1370, 2016 | 45 | 2016 |
A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Y Zhu, CH Chan, ZH Zheng, C Li, JY Zhong, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 65 (11), 3606-3616, 2018 | 16 | 2018 |
Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC C Li, CH Chan, Y Zhu, R Martins IEEE Transactions on Circuits and Systems I: Regular Paper 66 (1), 82 - 93, 2019 | 15 | 2019 |
A 17 Gb/s 10.7 pJ/b 4FSK transceiver system for point to point communication in 65 nm CMOS H Afzal, C Li, O Momeni 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 71-74, 2022 | 12 | 2022 |
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC G Wang, C Li, Y Zhu, J Zhong, Y Lu, CH Chan, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 65 (11), 3707-3719, 2018 | 5 | 2018 |
A highly efficient 165-GHz 4FSK 17-Gb/s transceiver system with frequency overlapping architecture in 65-nm CMOS H Afzal, C Li, O Momeni IEEE Journal of Solid-State Circuits 58 (11), 3113-3126, 2023 | 4 | 2023 |