3DVLSI with CoolCube process: An alternative path to scaling P Batude, C Fenouillet-Beranger, L Pasini, V Lu, F Deprat, L Brunet, ... 2015 Symposium on VLSI Technology (VLSI Technology), T48-T49, 2015 | 147 | 2015 |
3D sequential integration opportunities and technology optimization P Batude, B Sklenard, C Fenouillet-Beranger, B Previtali, C Tabone, ... IEEE International Interconnect Technology Conference, 373-376, 2014 | 70 | 2014 |
Monolithic 3D integration: A powerful alternative to classical 2D scaling M Vinet, P Batude, C Fenouillet-Beranger, F Clermidy, L Brunet, ... 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2014 | 67 | 2014 |
A comprehensive study of Monolithic 3D cell on cell design using commercial 2D tool O Billoint, H Sarhan, I Rayane, M Vinet, P Batude, C Fenouillet-Beranger, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 36 | 2015 |
An unbalanced area ratio study for high performance monolithic 3D integrated circuits H Sarhan, S Thuries, O Billoint, F Clermidy 2015 IEEE Computer Society Annual Symposium on VLSI, 350-355, 2015 | 17 | 2015 |
Technology scaling: The CoolCubeTM paradigm F Clermidy, O Billoint, H Sarhan, S Thuries 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015 | 16 | 2015 |
From 2D to monolithic 3D: Design possibilities, expectations and challenges O Billoint, H Sarhan, I Rayane, M Vinet, P Batude, C Fenouillet-Beranger, ... Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015 | 12 | 2015 |
3DCoB: A new design approach for Monolithic 3D Integrated Circuits H Sarhan, S Thuries, O Billoint, F Clermidy Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, 79-84, 2014 | 10 | 2014 |
Intermediate BEOL process influence on power and performance for 3DVLSI H Sarhan, S Thuries, O Billoint, F Deprat, AA De Sousa, P Batude, ... 2015 International 3D Systems Integration Conference (3DIC), TS1. 3.1-TS1. 3.5, 2015 | 8 | 2015 |
Temperature-aware adaptive task-mapping targeting uniform thermal distribution in MPSoC platforms H Sarhan, OK Eddash, M Raymond, A Wassal, Y Ismail 2010 International Conference on Energy Aware Computing, 1-3, 2010 | 8 | 2010 |
Novel 3D memory-centric NoC architecture for transaction-based SoC applications AG Wassal, HH Sarhan, A ElSherief 2011 Saudi International Electronics, Communications and Photonics …, 2011 | 7 | 2011 |
3D circuit design method H Sarhan, O Billoint, F Clermidy, S Thuries US Patent 9,922,151, 2018 | 5 | 2018 |
Compact interconnect approach for networks of neural cliques using 3D technology B Boguslawski, H Sarhan, F Heitzmann, F Seguin, S Thuries, O Billoint, ... 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 5 | 2015 |
A partitioning-free methodology for optimized gate-level monolithic 3D designs O Billoint, M Brocard, S Thuries, G Berhault, H Sarhan 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2017 | 3 | 2017 |
Combining Topological & Physical Pattern Recognition To Enhance Memory Chip Reliability S Hany, S Byun, H Sarhan, D Medhat, M ElRefaee, J Jang, B Jeong, ... 2020 IEEE International Integrated Reliability Workshop (IIRW), 1-4, 2020 | 1 | 2020 |
Design methodology and technology assessment for high-desnity 3D technologies H Sarhan Université Grenoble Alpes, 2015 | 1 | 2015 |
Automated Analog Design Constraint Checking How to achieve better performance reliability in analog circuits. H Sarhan, A Arriordaz | | 2019 |
Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits H Sarhan, S Thuries, O Billoint, F Clermidy Microelectronics Journal 60, 109-118, 2017 | | 2017 |
Optimization of TSV-based Crossbars for a 3D Memory-Centric Network-on-Chip HH Sarhan, AG Wassal Proceedings of the International Conference on Parallel and Distributed …, 2013 | | 2013 |
Today’s analog/RF designs need interconnect inductance extraction H Sarhan | | |