关注
Ramin Farjad
Ramin Farjad
未知所在单位机构
在 alumni.stanford.edu 的电子邮件经过验证
标题
引用次数
引用次数
年份
A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver
R Farjad-Rad, CKK Yang, MA Horowitz
IEEE Journal of Solid-State Circuits 35 (5), 757-764, 2000
3012000
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips
R Farjad-Rad, W Dally, HT Ng, R Senthinathan, MJE Lee, R Rathi, ...
IEEE Journal of Solid-State Circuits 37 (12), 1804-1812, 2002
2822002
A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling
CKK Yang, R Farjad-Rad, MA Horowitz
IEEE Journal of Solid-State Circuits 33 (5), 713-722, 1998
2641998
A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter
R Farjad-Rad, CKK Yang, MA Horowitz, TH Lee
IEEE Journal of Solid-State Circuits 34 (5), 580-585, 1999
2021999
Jitter transfer characteristics of delay-locked loops-theories and design techniques
MJE Lee, WJ Dally, T Greer, HT Ng, R Farjad-Rad, J Poulton, ...
IEEE Journal of Solid-State Circuits 38 (4), 614-621, 2003
1872003
High-speed signaling systems with adaptable pre-emphasis and equalization
JL Zerbe, FF Chen, A Ho, R Farjad-Rad, JW Poulton, KS Donnelly, ...
US Patent 9,137,063, 2015
1552015
Low-power low-jitter variable delay timing circuit
WJ Dally, R Farjad-Rad, TJ Stone, X Yu, JW Poulton
US Patent 6,316,987, 2001
1442001
Phase controlled oscillator
WJ Dally, R Farjad-Rad, JW Poulton, TH Greer III, HT Ng, TJ Stone
US Patent 6,617,936, 2003
972003
Analog N-tap FIR receiver equalizer
R Farjad-Rad, TH Lee
US Patent 7,167,517, 2007
782007
A second-order semidigital clock recovery circuit based on injection locking
HT Ng, R Farjad-Rad, MJE Lee, WJ Dally, T Greer, J Poulton, ...
IEEE Journal of Solid-State Circuits 38 (12), 2101-2110, 2003
762003
0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization
R Farjad-Rad, HT Ng, MJE Lee, R Senthinathan, WJ Dally, A Nguyen, ...
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2003
742003
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os
R Farjad-Rad, A Nguyen, JM Tran, T Greer, J Poulton, WJ Dally, ...
IEEE Journal of Solid-State Circuits 39 (9), 1553-1561, 2004
722004
Adaptive receive-side equalization
R Farjad-Rad
US Patent 7,639,736, 2009
712009
Fast-lock clock-data recovery system
J Edmondson, J Eble, R Farjad-Rad, S Barakat
US Patent App. 11/016,513, 2006
702006
A 7.5 Gb/s 10-tap DFE receiver with first tap partial response, spectrally gated adaptation, and 2nd-order data-filtered CDR
BS Leibowitz, J Kizer, H Lee, F Chen, A Ho, M Jeeradit, A Bansal, T Greer, ...
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
692007
Wide-range multi-phase clock generator
R Farjad-Rad, JW Poulton, J Eble, TH Greer III, R Palmer
US Patent 7,319,345, 2008
642008
Phase detector for clock synchronization and recovery
R Farjad-Rad, RJ Drost
US Patent 5,799,048, 1998
641998
Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining
R Farjadrad, R Shirani
US Patent 7,577,891, 2009
632009
CMOS high-speed I/Os-present and future
MJE Lee, WJ Dally, R Farjad-Rad, HT Ng, R Senthinathan, J Edmondson, ...
Proceedings 21st International Conference on Computer Design, 454-461, 2003
482003
Phase controlled oscillator circuit with input signal coupler
WJ Dally, R Farjad-Rad, JW Poulton, TH Greer III, HT Ng, TJ Stone
US Patent 6,861,916, 2005
472005
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