A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... IEEE Journal of Solid-State Circuits 48 (12), 3049-3058, 2013 | 403 | 2013 |
22.1 a 90gs/s 8b 667mw 64× interleaved sar adc in 32nm digital soi cmos L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 221 | 2014 |
Single-photon detection beyond 1 μm: performance of commercially available germanium photodiodes A Lacaita, PA Francese, F Zappa, S Cova Applied optics 33 (30), 6902-6918, 1994 | 140 | 1994 |
A 24–72-GS/s 8-b time-interleaved SAR ADC with 2.0–3.3-pJ/conversion and> 30 dB SNDR at Nyquist in 14-nm CMOS FinFET L Kull, D Luu, C Menolfi, M Braendli, PA Francese, T Morf, M Kossel, ... IEEE Journal of Solid-State Circuits 53 (12), 3508-3516, 2018 | 132 | 2018 |
A 200MS/s 14b 97mW DAC in 0.18/spl mu/m CMOS Q Huang, PA Francese, C Martelli, J Nielsen 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 118 | 2004 |
HERMES Core–A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 104 | 2021 |
28.5 A 10b 1.5 GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET L Kull, D Luu, C Menolfi, M Braendli, PA Francese, T Morf, M Kossel, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 474-475, 2017 | 103 | 2017 |
A 1.8 V 1.0 GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency RC Taft, PA Francese, MR Tursi, O Hidri, A MacKenzie, T Hohn, P Schmitz, ... IEEE Journal of Solid-State Circuits 44 (12), 3294-3304, 2009 | 102 | 2009 |
A 4.6W/mm2power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and …, 2013 | 101 | 2013 |
Implementation of low-power 6–8 b 30–90 GS/s time-interleaved ADCs with optimized input bandwidth in 32 nm CMOS L Kull, J Pliva, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, ... IEEE Journal of Solid-State Circuits 51 (3), 636-648, 2016 | 91 | 2016 |
A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7 W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... IEEE International Solid-State Circuits Conference, 2014 | 91 | 2014 |
A 2.6 mW/Gbps 12.5 Gbps RX with 8-tap switched-capacitor DFE in 32 nm CMOS T Toifl, C Menolfi, M Ruegg, R Reutemann, D Dreps, T Beukema, A Prati, ... IEEE Journal of Solid-State Circuits 47 (4), 897-910, 2012 | 84 | 2012 |
Single-photon optical-time-domain reflectometer at 1.3 μm with 5-cm resolution and high sensitivity AL Lacaita, PA Francese, SD Cova, G Riparmonti Optics letters 18 (13), 1110-1112, 1993 | 83 | 1993 |
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference M Le Gallo, R Khaddam-Aljameh, M Stanisavljevic, A Vasilopoulos, ... Nature Electronics 6 (9), 680-693, 2023 | 78 | 2023 |
A 112Gb/S 2.6 pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS C Menolfi, M Braendli, PA Francese, T Morf, A Cevrero, M Kossel, L Kull, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 104-106, 2018 | 76 | 2018 |
HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, M Brändli, ... IEEE Journal of Solid-State Circuits 57 (4), 1027-1038, 2022 | 74 | 2022 |
A 64-Gb/s 1.4-pJ/b NRZ optical receiver data-path in 14-nm CMOS FinFET I Ozkaya, A Cevrero, PA Francese, C Menolfi, T Morf, M Brändli, ... IEEE Journal of Solid-State Circuits 52 (12), 3458-3473, 2017 | 68 | 2017 |
A 10 W on-chip switched capacitor voltage regulator with feedforward regulation capability for granular microprocessor power delivery TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... IEEE Transactions on Power Electronics 32 (1), 378-393, 2016 | 66 | 2016 |
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... 2013 Symposium on VLSI Circuits, C260-C261, 2013 | 65 | 2013 |
6.1 A 100Gb/s 1.1 pJ/b PAM-4 RX with dual-mode 1-tap PAM-4/3-tap NRZ speculative DFE in 14nm CMOS FinFET A Cevrero, I Ozkaya, PA Francese, M Brandli, C Menolfi, T Morf, M Kossel, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 112-114, 2019 | 64 | 2019 |