| A 530 Mpixels/s 4096x2160@ 60fps H.264/AVC high profile video decoder chip D Zhou, J Zhou, X He, J Zhu, J Kong, P Liu, S Goto Solid-State Circuits, IEEE Journal of 46 (4), 777-788, 2011 | 83 | 2011 |
| A 530mpixels/s 4096x2160@ 60fps H.264/AVC high profile video decoder chip D Zhou, J Zhou, X He, J Kong, J Zhu, P Liu, S Goto Symposium on VLSI Circuits (June 2010), 2010 | 83 | 2010 |
| High-throughput power-efficient VLSI architecture of fractional motion estimation for Ultra-HD HEVC video encoding G He, D Zhou, Y Li, Z Chen, T Zhang, S Goto Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 23 (12 …, 2015 | 81 | 2015 |
| Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks S Wang, D Zhou, X Han, T Yoshimura Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 72 | 2017 |
| Ultra-high-throughput VLSI architecture of H.265/HEVC CABAC encoder for UHDTV applications D Zhou, J Zhou, W Fei, S Goto Circuits and Systems for Video Technology, IEEE Transactions on 25 (3), 497-507, 2015 | 70 | 2015 |
| A low-complexity HEVC intra prediction algorithm based on level and mode filtering H Sun, D Zhou, S Goto 2012 IEEE International Conference on Multimedia and Expo, 1085-1090, 2012 | 69 | 2012 |
| An optimized MC interpolation architecture for HEVC Z Guo, D Zhou, S Goto 2012 IEEE International Conference on Acoustics, Speech and Signal …, 2012 | 59 | 2012 |
| An SDRAM controller optimized for high definition video coding application J Zhu, P Liu, D Zhou Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on …, 2008 | 49 | 2008 |
| CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks X Han, D Zhou, S Wang, S Kimura 2016 IEEE 34th International Conference on Computer Design (ICCD), 320-327, 2016 | 47 | 2016 |
| A 1.59 Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder J Zhou, D Zhou, G He, S Goto VLSI Circuits (VLSIC), 2013 Symposium on, C286-C287, 2013 | 45 | 2013 |
| A new reference frame recompression algorithm and its VLSI architecture for UHDTV video codec L Guo, D Zhou, S Goto IEEE Transactions on Multimedia 16 (8), 2323-2332, 2014 | 44 | 2014 |
| Low-complexity rate-distortion optimization algorithms for HEVC intra prediction Z Sheng, D Zhou, H Sun, S Goto MultiMedia Modeling: 20th Anniversary International Conference, MMM 2014 …, 2014 | 44 | 2014 |
| A 115mw 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm cmos X Peng, Z Chen, X Zhao, D Zhou, S Goto IEEE Asian Solid-State Circuits Conference 2011, 317-320, 2011 | 41 | 2011 |
| An advanced hierarchical motion estimation scheme with lossless frame recompression and early-level termination for beyond high-definition video coding X Bao, D Zhou, P Liu, S Goto IEEE Transactions on Multimedia 14 (2), 237-249, 2011 | 40 | 2011 |
| A lossless frame recompression scheme for reducing DRAM power in video encoding X Bao, D Zhou, S Goto Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International …, 2010 | 38 | 2010 |
| 14.7 A 4Gpixel/s 8/10b H. 265/HEVC video decoder chip for 8K Ultra HD applications D Zhou, S Wang, H Sun, J Zhou, J Zhu, Y Zhao, J Zhou, S Zhang, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 266-268, 2016 | 36 | 2016 |
| A combined SAO and de-blocking filter architecture for HEVC video decoder J Zhu, D Zhou, G He, S Goto 2013 IEEE International Conference on Image Processing, 1967-1971, 2013 | 33 | 2013 |
| A 1080p@ 60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective D Zhou, Z You, J Zhu, J Kong, Y Hong, X Chen, X He, C Xu, H Zhang, ... VLSI Circuits, 2009 Symposium on, 262-263, 2009 | 33 | 2009 |
| A high-performance CABAC encoder architecture for HEVC and H.264/AVC J Zhou, D Zhou, W Fei, S Goto Image Processing (ICIP), 2013 20th IEEE International Conference on, 1568-1572, 2013 | 30 | 2013 |
| A hardware-efficient dual-standard VLSI architecture for MC interpolation in AVS and H.264 D Zhou, P Liu Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on …, 2007 | 28 | 2007 |
satoshi goto早稲田大学教授在 waseda.jp 的电子邮件经过验证
