| Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration H Genc, S Kim, A Amid, A Haj-Ali, V Iyer, P Prakash, J Zhao, D Grubb, ... 2021 58th ACM/IEEE Design Automation Conference (DAC), 769-774, 2021 | 226 | 2021 |
| Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architectures H Genc, A Haj-Ali, V Iyer, A Amid, H Mao, J Wright, C Schmidt, J Zhao, ... arXiv preprint arXiv:1911.09925 3 (25), 15-17, 2019 | 101 | 2019 |
| A dual-core risc-v vector processor with on-chip fine-grain power management in 28-nm fd-soi JC Wright, C Schmidt, B Keller, DP Dabbelt, J Kwak, V Iyer, N Mehta, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (12 …, 2020 | 24 | 2020 |
| Yakun Sophia Shao, Borivoje Nikolic, Ion Stoica, and Krste Asanovic. 2019. Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning … H Genc, A Haj-Ali, V Iyer, A Amid, H Mao, J Wright, C Schmidt, J Zhao, ... arXiv preprint arXiv:1911.09925, 0 | 11 | |
| RTL-Repair: Fast Symbolic Repair of Hardware Design Code K Laeufer, B Fajardo, A Ahuja, V Iyer, B Nikolić, K Sen Proceedings of the 29th ACM International Conference on Architectural …, 2024 | 6 | 2024 |
| Simulator independent coverage for RTL hardware languages K Laeufer, V Iyer, D Biancolin, J Bachrach, B Nikolić, K Sen Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 5 | 2023 |
| Yakun Sophia Shao, Borivoje Nikolić, Ion Stoica, and Krste Asanović. 2019 H Genç, A Haj-Ali, V Iyer, A Amid, H Mao, JC Wright, C Schmidt, J Zhao, ... Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations …, 2019 | 5 | 2019 |
| Design and Application of a Co-Simulation Framework for Chisel R Lund MA thesis. EECS Department, University of California, Berkeley, 2021 | 2 | 2021 |
| Dynamic verification library for chisel YC Tsai Master's thesis, EECS Department, University of California, Berkeley, 2021 | 2 | 2021 |
| RTL bug localization through LTL specification mining (WIP) V Iyer, D Kim, B Nikolic, SA Seshia Proceedings of the 17th ACM-IEEE International Conference on Formal Methods …, 2019 | 1 | 2019 |
| An Architectural Power Model for Networks on Chip A Agrawal | | 2023 |
| Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas A Ardakani, M Kang, K He, V Iyer, S Moon, J Wawrzynek | | |
