Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications MR Tripathy, AK Singh, A Samad, S Chander, K Baral, PK Singh, S Jit IEEE Transactions on Electron Devices 67 (3), 1285-1292, 2020 | 119 | 2020 |
2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure S Kumar, K Singh, S Chander, E Goel, PK Singh, K Baral, B Singh, S Jit IEEE Transactions on Electron Devices 65 (1), 331-338, 2017 | 68 | 2017 |
Temperature analysis of Ge/Si heterojunction SOI-tunnel FET S Chander, SK Sinha, S Kumar, PK Singh, K Baral, K Singh, S Jit Superlattices and Microstructures 110, 162-170, 2017 | 60 | 2017 |
Heterojunction fully depleted SOI-TFET with oxide/source overlap S Chander, B Bhowmick, S Baishya Superlattices and Microstructures 86, 43-50, 2015 | 54 | 2015 |
A two-dimensional gate threshold voltage model for a heterojunction SOI-tunnel FET with oxide/source overlap S Chander, S Baishya IEEE Electron device letters 36 (7), 714-716, 2015 | 47 | 2015 |
Comprehensive review on electrical noise analysis of TFET structures S Chander, SK Sinha, R Chaudhary Superlattices and Microstructures 161, 107101, 2022 | 42 | 2022 |
Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs S Chander, S Baishya, SK Sinha, S Kumar, PK Singh, K Baral, ... Superlattices and Microstructures 131, 30-39, 2019 | 40 | 2019 |
Reliability models with priority for operation and repair with arrival time of server S Chander Pure and Applied Mathematika Sciences 61 (1-2), 9-22, 2005 | 34 | 2005 |
Reliability and economic analysis of 2-out-of-3 redundant system with priority to repair S Chander, RK Bhardwaj African J. of Maths and comp. sci 2 (11), 230-236, 2009 | 33 | 2009 |
Simulation study and comparative analysis of some TFET structures with a novel partial-ground-plane (PGP) based TFET on SELBOX structure AK Singh, MR Tripathy, S Chander, K Baral, PK Singh, S Jit Silicon 12, 2345-2354, 2020 | 30 | 2020 |
Profit analysis of single-unit reliability models with repair at different failure modes S Chander, RK Bansal Proc. INCRESE IIT Kharagpur, India, 577-587, 2005 | 30 | 2005 |
Ge-source based L-shaped tunnel field effect transistor for low power switching application S Chander, SK Sinha, R Chaudhary, A Singh Silicon, 1-14, 2021 | 29 | 2021 |
Performance analysis of heterojunction tunnel FET device with variable temperature IA Pindoo, SK Sinha, S Chander Applied Physics A 127, 1-10, 2021 | 28 | 2021 |
Improvement of electrical characteristics of SiGe source based tunnel FET device IA Pindoo, SK Sinha, S Chander Silicon 13 (9), 3209-3215, 2021 | 27 | 2021 |
Behaviour of β-Cyfluthrin and Imidacloprid in Mustard Crop: Alternative Insecticide for Aphid Control. M Gopal, I Mukherjee, S Chander Bulletin of Environmental Contamination & Toxicology 68 (3), 2002 | 25 | 2002 |
Investigation of DC performance of Ge-source pocket silicon-on-insulator tunnel field effect transistor in nano regime SK Sinha, S Chander International Journal of Nanoparticles 13 (1), 13-20, 2021 | 21 | 2021 |
Reliability modeling of 2-out-of-3 redundant system subject to degradation after repair S Chander, M Singh Journal of Reliability and Statistical Studies, 91-104, 2009 | 20 | 2009 |
Stochastic analysis of non-identical units reliability models with priority and different modes of failure MS Kadyan, S Chander, AS Grewal Decision and Mathematical Sciences 9 (1-3), 59-82, 2004 | 20 | 2004 |
Two-dimensional model of a heterojunction silicon-on-insulator tunnel field effect transistor S Chander, S Baishya Superlattices and Microstructures 90, 176-183, 2016 | 19 | 2016 |
Reliability and cost benefit analysis of 2-out-of-3 redundant system with general distribution of repair and waiting time RK Bhardwaj, S Chander DIAS Technology Review: The International Journal for Business & IT 4 (1), 28-35, 2007 | 19 | 2007 |