| Carbon Nano Tube Field Effect Transistors Based Ternary Ex- OR and Ex-NOR Gates AS Kavitha Patcha , Sarada Musala , K. Vijayavardhan, Y. Sudha Vani Current Nanoscience, 2016 | 34 | 2016 |
| A low voltage capacitor based current controlled sense amplifier for input offset compensation YS Vani, NU Rani, R Vaddi 2017 International SoC Design Conference (ISOCC), 23-24, 2017 | 10 | 2017 |
| Design and performance benchmarking of hybrid tunnel FET/STT-MTJ-based logic in-memory designs for energy efficiency SV Yamani, NU Rani, R Vaddi IEEE Transactions on Magnetics 58 (4), 1-11, 2022 | 3 | 2022 |
| Design of three stage Dynamic Comparator with tail transistor using 20nm FinFET technology for ADCs SV Yamani, HKRV Kudulla, SS Rao 2022 International Conference on Computing, Communication and Power …, 2022 | 3 | 2022 |
| An energy-efficient hybrid tunnel FET based STT-MRAM memory cell design at low VDD SV Yamani, NU Rani, R Vaddi International Journal of Electronics 109 (3), 537-551, 2022 | 2 | 2022 |
| A 128kb ram design with capacitor-based offset compensation and double-diode based read assist circuits at low V Dd SV Yamani, NU Rani, R Vaddi Journal of Scientific & Industrial Research 79 (9), 788-793, 2020 | 1 | 2020 |
| Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic SV Yamani, MVS RamPrasad, G Dinesh, EY Yeshaswila, CR Teja, ... Analog Integrated Circuits and Signal Processing 119 (1), 151-163, 2024 | | 2024 |
| Area Efficient Sparse-4 Diminished-1 Modulo 2n + 1 Adder SV Yamani, HKRV Kudulla, DD Bhavani 2024 IEEE Wireless Antenna and Microwave Symposium (WAMS), 1-7, 2024 | | 2024 |
| Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines PR Ramya, YS Vani International Journal of Reconfigurable and Embedded Systems 2 (1), 21, 2013 | | 2013 |
| Design and Implementation of Energy Efficient Memory and Logic Circuits Exploring Post CMOS Devices at Low VDD SV YAMANI Guntur, 0 | | |
