| Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm YC Tsao, K Choi IEEE transactions on very large scale integration (vlsi) systems 20 (2), 366-371, 2010 | 124 | 2010 |
| Area-efficient VLSI implementation for parallel linear-phase FIR digital filters of odd length based on fast FIR algorithm YC Tsao, K Choi IEEE Transactions on Circuits and Systems II: Express Briefs 59 (6), 371-375, 2012 | 79 | 2012 |
| Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length YC Tsao, K Choi 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 998-1001, 2012 | 15 | 2012 |
| Hardware-efficient parallel FIR digital filter structures for symmetric convolutions YC Tsao, K Choi 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2301-2304, 2011 | 13 | 2011 |
| Pipeline power reduction through single comparator-based clock gating W Wang, YC Tsao, K Choi, SM Park, MK Chung 2009 International SoC Design Conference (ISOCC), 480-483, 2009 | 13 | 2009 |
| A simplified flow for synthesizing digital FIR filters based on common subexpression elimination YC Tsao, K Choi 2010 International SoC Design Conference, 174-177, 2010 | 2 | 2010 |
| Cost reduction on high-speed 1D IDCT architecture based on time rescaling YC Tsao, K Choi 2011 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, 1-6, 2011 | 1 | 2011 |
| Hardware-efficient VLSI implementation for parallel linear-phase digital FIR filter YC Tsao Illinois Institute of Technology, 2011 | | 2011 |
