| A 43-mW MASH 2-2 CT Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS A Edward, Q Liu, C Briseno-Vidrios, M Kinyua, EG Soenen, AI Karşılayan, ... IEEE Journal of Solid-State Circuits 52 (2), 448-459, 2016 | 48 | 2016 |
| A low-power digitizer for back-illuminated 3-D-stacked CMOS image sensor readout with passing window and double auto-zeroing techniques Q Liu, A Edward, M Kinyua, EG Soenen, J Silva-Martinez IEEE Journal of Solid-State Circuits 52 (6), 1591-1604, 2017 | 30 | 2017 |
| A 245-mA digitally assisted dual-loop low-dropout regulator D Zhou, J Jiang, Q Liu, EG Soenen, M Kinyua, J Silva-Martinez IEEE Journal of Solid-State Circuits 55 (8), 2140-2150, 2020 | 25 | 2020 |
| A 44-fJ/conversion step 200-MS/s pipeline ADC employing current-mode MDACs C Briseno-Vidrios, D Zhou, S Prakash, Q Liu, A Edward, EG Soenen, ... IEEE Journal of Solid-State Circuits 53 (11), 3280-3292, 2018 | 24 | 2018 |
| A continuous-time MASH 1-1-1 Delta–Sigma modulator with FIR DAC and encoder-embedded loop-unrolling quantizer in 40-nm CMOS Q Liu, A Edward, D Zhou, J Silva-Martinez IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (4), 756-767, 2017 | 23 | 2017 |
| A 2× 20W 0.0013% THD+ N class-D audio amplifier with consistent performance up to maximum power level E Cope, J Aschieri, T Lai, F Zhao, W Grandfield, M Clifford, P Rathfelder, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 56-58, 2018 | 20 | 2018 |
| Gain‐boosted dynamic amplifier for pipelined‐SAR ADCs M Zhang, Q Liu, X Fan Electronics Letters 53 (11), 708-709, 2017 | 17 | 2017 |
| A 35 dBm output power and 38 dB linear gain PA with 44.9% peak PAE at 1.9 GHz in 40 nm CMOS H Qian, Q Liu, J Silva-Martinez, S Hoyos IEEE Journal of Solid-State Circuits 51 (3), 587-597, 2016 | 17 | 2016 |
| A 13-bit 260MS/s power-efficient pipeline ADC using a current-reuse technique and interstage gain and nonlinearity errors calibration D Zhou, C Briseno-Vidrios, J Jiang, C Park, Q Liu, EG Soenen, M Kinyua, ... IEEE Transactions on Circuits and Systems I: Regular Papers 66 (9), 3373-3383, 2019 | 15 | 2019 |
| A 13bit 200MS/S pipeline ADC with current-mode MDACs C Briseno-Vidrios, D Zhou, S Prakash, Q Liu, A Edward, J Silva-Martinez 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 9 | 2017 |
| Analog to digital converter compatible with image sensor readout Q Liu, M Kinyua, E Soenen US Patent 9,529,336, 2016 | 7 | 2016 |
| High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications Q Liu, A Edward, C Briseno-Vidrios, N Rashidi, J Silva-Martinez 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 1 | 2017 |
| IEEE CIRCUITS AND SYSTEMS SOCIETY JM DE LA ROSA, Y HA, E BONIZZONI, AJ ACOSTA, J ANDERS, ... | | 2020 |
| Design Techniques for Mash Continuous-Time Delta-Sigma Modulators Q Liu, A Edward, C Briseno-Vidrios, J Silva-Martinez Springer International Publishing, 2018 | | 2018 |
| MASH 4-0 CTΔΣM with Fully Digital Quantization Noise Reduction Algorithm Q Liu, A Edward, C Briseno-Vidrios, J Silva-Martinez, Q Liu, A Edward, ... Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 129-157, 2018 | | 2018 |
| Design of Continuous-Time Delta-Sigma Modulators Q Liu, A Edward, C Briseno-Vidrios, J Silva-Martinez, Q Liu, A Edward, ... Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 35-76, 2018 | | 2018 |
| Analog-to-Digital and Digital-to-Analog Converters Q Liu, A Edward, C Briseno-Vidrios, J Silva-Martinez, Q Liu, A Edward, ... Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 7-18, 2018 | | 2018 |
| Delta-Sigma Modulators Q Liu, A Edward, C Briseno-Vidrios, J Silva-Martinez, Q Liu, A Edward, ... Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 19-33, 2018 | | 2018 |
| Design of MASH Continuous-Time Delta-Sigma Modulators Q Liu, A Edward, C Briseno-Vidrios, J Silva-Martinez, Q Liu, A Edward, ... Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 77-100, 2018 | | 2018 |
| MASH 1-1-1 CTΔΣM with FIR DAC and Loop-Unrolling Quantizer Q Liu, A Edward, C Briseno-Vidrios, J Silva-Martinez, Q Liu, A Edward, ... Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 159-185, 2018 | | 2018 |
