| A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS G Balamurugan, J Kennedy, G Banerjee, JE Jaussi, M Mansuri, ... IEEE Journal of Solid-State Circuits 43 (4), 1010-1019, 2008 | 210 | 2008 |
| 8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew JE Jaussi, G Balamurugan, DR Johnson, B Casper, A Martin, J Kennedy, ... IEEE Journal of Solid-State Circuits 40 (1), 80-88, 2005 | 150 | 2005 |
| Modeling and analysis of high-speed I/O links G Balamurugan, B Casper, JE Jaussi, M Mansuri, F O'Mahony, J Kennedy IEEE transactions on advanced packaging 32 (2), 237-247, 2009 | 117 | 2009 |
| Wireline receiver circuitry having collaborative timing recovery T Musah, G Keskin, G Balamurugan, JE Jaussi, BK Casper US Patent 9,374,250, 2016 | 112 | 2016 |
| A scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-lane parallel I/O in 32-nm CMOS M Mansuri, JE Jaussi, JT Kennedy, TC Hsueh, S Shekhar, ... IEEE Journal of solid-state circuits 48 (12), 3229-3242, 2013 | 112 | 2013 |
| A 4710 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS F O'Mahony, JE Jaussi, J Kennedy, G Balamurugan, M Mansuri, ... IEEE journal of solid-state circuits 45 (12), 2828-2837, 2010 | 112 | 2010 |
| A 130-nm 6-GHz 256/spl times/32 bit leakage-tolerant register file RK Krishnamurthy, A Alvandpour, G Balamurugan, NR Shanbhag, ... IEEE Journal of Solid-State Circuits 37 (5), 624-632, 2002 | 107 | 2002 |
| The twin-transistor noise-tolerant dynamic circuit technique G Balamurugan, NR Shanbhag IEEE Journal of Solid-State Circuits 36 (2), 273-280, 2001 | 90 | 2001 |
| A 3-D-integrated silicon photonic microring-based 112-Gb/s PAM-4 transmitter with nonlinear equalization and thermal control H Li, G Balamurugan, T Kim, MN Sakib, R Kumar, H Rong, J Jaussi, ... IEEE Journal of Solid-State Circuits 56 (1), 19-29, 2020 | 87 | 2020 |
| Strong Injection Locking in Low- LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver S Shekhar, M Mansuri, F O'Mahony, G Balamurugan, JE Jaussi, ... IEEE Transactions on Circuits and Systems I: Regular Papers 56 (8), 1818-1829, 2009 | 86 | 2009 |
| A 112 Gb/s PAM4 silicon photonics transmitter with microring modulator and CMOS driver H Li, G Balamurugan, M Sakib, J Sun, J Driscoll, R Kumar, H Jayatilleka, ... Journal of Lightwave Technology 38 (1), 131-138, 2020 | 82 | 2020 |
| Future microprocessor interfaces: Analysis, design and optimization B Casper, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, F O'Mahony, ... 2007 IEEE Custom Integrated Circuits Conference, 479-486, 2007 | 76 | 2007 |
| A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS H Li, G Balamurugan, J Jaussi, B Casper ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 69 | 2018 |
| A 4–32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS T Musah, JE Jaussi, G Balamurugan, S Hyvonen, TC Hsueh, G Keskin, ... IEEE Journal of Solid-State Circuits 49 (12), 3079-3090, 2014 | 66 | 2014 |
| The future of electrical I/O for microprocessors F O'Mahony, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, ... 2009 International Symposium on VLSI Design, Automation and Test, 31-34, 2009 | 61 | 2009 |
| A 27Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS F O'Mahony, S Shekhar, M Mansuri, G Balamurugan, JE Jaussi, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 59 | 2008 |
| A 112 Gb/s PAM4 transmitter with silicon photonics microring modulator and CMOS driver H Li, G Balamurugan, M Sakib, J Sun, J Driscoll, R Kumar, H Jayatilleka, ... 2019 Optical Fiber Communications Conference and Exhibition (OFC), 1-3, 2019 | 51 | 2019 |
| Energy-efficient dynamic circuit design in the presence of crosstalk noise G Balamurugan, NR Shanbhag Proceedings of the 1999 international symposium on Low power electronics and …, 1999 | 49 | 1999 |
| Silicon photonic microring-based 4× 112 Gb/s WDM transmitter with photocurrent-based thermal control in 28-nm CMOS J Sharma, Z Xuan, H Li, T Kim, R Kumar, MN Sakib, CM Hsu, C Ma, ... IEEE Journal of Solid-State Circuits 57 (4), 1187-1198, 2021 | 46 | 2021 |
| Modeling and mitigation of jitter in multiGbps source-synchronous I/O links G Balamurugan, N Shanbhag Proceedings 21st International Conference on Computer Design, 254-260, 2003 | 45 | 2003 |
