Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ... IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018 | 128 | 2018 |
BiometricNet: Deep learning based biometric identification using wrist-worn PPG L Everson, D Biswas, M Panwar, D Rodopoulos, A Acharyya, CH Kim, ... 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 70 | 2018 |
Time and workload dependent device variability in circuit simulations D Rodopoulos, SB Mahato, VV de Almeida Camargo, B Kaczer, ... 2011 IEEE International Conference on IC Design & Technology, 1-4, 2011 | 46 | 2011 |
Design-technology co-optimization for OxRRAM-based synaptic processing unit A Mallik, D Garbin, A Fantini, D Rodopoulos, R Degraeve, J Stuijt, AK Das, ... 2017 Symposium on VLSI Technology, T178-T179, 2017 | 38 | 2017 |
Sub-word parallel precision-scalable MAC engines for efficient embedded DNN inference L Mei, M Dandekar, D Rodopoulos, J Constantin, P Debacker, ... 2019 IEEE international conference on artificial intelligence circuits and …, 2019 | 37 | 2019 |
Atomistic Pseudo-Transient BTI Simulation with Inherent Workload Memory D Rodopoulos, P Weckx, M Noltsis, F Catthoor, D Soudris IEEE, 2014 | 34 | 2014 |
Low track height standard cell design in iN7 using scaling boosters SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ... Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 31 | 2017 |
Semiconductor cell configured to perform logic operations D Garbin, D Rodopoulos, P Debacker, P Raghavan US Patent App. 15/820,239, 2018 | 30 | 2018 |
BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations G Smaragdos, G Chatzikonstantis, R Kukreja, H Sidiropoulos, ... Journal of neural engineering 14 (6), 066008, 2017 | 27 | 2017 |
Tackling performance variability due to RAS mechanisms with PID-controlled DVFS D Rodopoulos, F Catthoor, D Soudris IEEE Computer Architecture Letters 14 (2), 156-159, 2014 | 23 | 2014 |
Performance analysis of accelerated biophysically-meaningful neuron simulations G Smaragdos, G Chatzikostantis, S Nomikou, D Rodopoulos, I Sourdis, ... 2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016 | 14 | 2016 |
Complexity-reduced simulation of circuit reliability P Weckx, D Rodopoulos, B Kaczer, F Catthoor US Patent App. 15/081,635, 2016 | 13 | 2016 |
Capturing true workload dependency of bti-induced degradation in cpu components D Stamoulis, S Corbetta, D Rodopoulos, P Weckx, P Debacker, BH Meyer, ... Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 373-376, 2016 | 13 | 2016 |
Optimal mapping of inferior olive neuron simulations on the single-chip cloud computer D Rodopoulos, G Chatzikonstantis, A Pantelopoulos, D Soudris, ... 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 13 | 2014 |
Classification framework for analysis and modeling of physically induced reliability violations D Rodopoulos, G Psychou, MM Sabry, F Catthoor, A Papanikolaou, ... ACM Computing Surveys (CSUR) 47 (3), 1-33, 2015 | 12 | 2015 |
Classification of resilience techniques against functional errors at higher abstraction layers of digital systems G Psychou, D Rodopoulos, MM Sabry, T Gemmeke, D Atienza, TG Noll, ... ACM Computing Surveys (CSUR) 50 (4), 1-38, 2017 | 10 | 2017 |
Optimizing extended hodgkin-huxley neuron model simulations for a xeon/xeon phi node G Chatzikonstantis, D Rodopoulos, C Strydis, CI De Zeeuw, D Soudris IEEE Transactions on Parallel and Distributed Systems 28 (9), 2581-2594, 2017 | 10 | 2017 |
Efficient reliability analysis of processor datapath using atomistic bti variability models D Stamoulis, D Rodopoulos, BH Meyer, D Soudris, F Catthoor, Z Zilic Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 57-62, 2015 | 10 | 2015 |
Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations D Rodopoulos, D Stamoulis, G Lyras, D Soudris, F Catthoor 2014 IEEE International Conference on IC Design & Technology, 1-4, 2014 | 10 | 2014 |
Control plane organization for flexible digital data plane F Catthoor, P Raghavan, D Garbin, D Rodopoulos, O Zografos US Patent 10,802,743, 2020 | 9 | 2020 |