| A 4.68 Gb/s belief propagation polar decoder with bit-splitting register file YS Park, Y Tao, S Sun, Z Zhang 2014 IEEE Symposium on VLSI Circuits, 1-2, 2014 | 110 | 2014 |
| A configurable successive-cancellation list polar decoder using split-tree architecture Y Tao, SG Cho, Z Zhang IEEE Journal of Solid-State Circuits 56 (2), 612-623, 2021 | 51 | 2021 |
| A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating YS Park, Y Tao, Z Zhang IEEE Journal of Solid-State Circuits 50 (2), 464-475, 2014 | 38 | 2014 |
| LDPC post-processor architecture and method for low error floor conditions Y Tao, J Kwong US Patent 9,793,923, 2017 | 29 | 2017 |
| A 2.4 mm 2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4× 4 256-QAM MIMO in 65nm CMOS CH Chen, W Tang, Y Tao, Z Zhang 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 24 | 2015 |
| DNC-Aided SCL-Flip Decoding of Polar Codes Y Tao, Z Zhang 2021 IEEE Global Communications Conference, 2021 | 23 | 2021 |
| High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders Y Tao, YS Park, Z Zhang 2012 IEEE International Symposium on Circuits and Systems, 2625-2628, 2012 | 23 | 2012 |
| A 1.15 Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating YS Park, Y Tao, Z Zhang 2013 IEEE International Solid-State Circuits Conference (ISSCC), 422-423, 2013 | 22 | 2013 |
| Part-based structured representation learning for person re-identification Y Li, H Yao, T Zhang, C Xu ACM Transactions on Multimedia Computing, Communications, and Applications …, 2020 | 18 | 2020 |
| High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder Y Tao, C Choi 2022 IEEE International Symposium on Circuits and Systems, 2022 | 14 | 2022 |
| Algorithm-Architecture Co-Design for Domain-Specific Accelerators in Communication and Artificial Intelligence Y Tao PhD Dissertation, University of Michigan Ann Arbor, 2022 | 14 | 2022 |
| Integrated Memristor Network for Physiological Signal Processing L Cai, L Yu, W Yue, Y Zhu, Z Yang, Y Li, Y Tao*, Y Yang* Advanced Electronic Materials, 2300021, 2023 | 13 | 2023 |
| HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer Y Tao, Z Zhang 54th IEEE/ACM International Symposium on Microarchitecture (MICRO), 845-856, 2021 | 7 | 2021 |
| Efficient in situ error detection enabling diverse path coverage CH Chen, Y Tao, Z Zhang 2013 IEEE International Symposium on Circuits and Systems, 773-776, 2013 | 7 | 2013 |
| Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm L Yu, Z Jing, Y Yang*, Y Tao* 2022 IEEE International Symposium on Circuits and Systems, 2022 | 5 | 2022 |
| Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes Y Tao, S Sun, Z Zhang IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) 66 (10 …, 2019 | 5 | 2019 |
| Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search L Cai, J Wang, L Yu, B Yan, Y Tao*, Y Yang* 2023 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2023 | 3 | 2023 |
| Automated estimation of human age, gender and expression Y Tao Stanford Digital Image Processing, 4, 2014 | 3 | 2014 |
| A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS Y Tao, SG Cho, Z Zhang 2019 IEEE Symposium on VLSI Circuits (VLSI), C240-C241, 2019 | 2 | 2019 |
| Seizure detection using dynamic memristor-based reservoir computing and leaky integrate-and-fire neuron for post-processing Z Yang, K Liu, R Yuan, X Wu, L Cai, T Zhang, Y Tao*, Y Jin, Y Yang* APL Machine Learning 1 (4), 2023 | 1 | 2023 |
