Novel low power comparator design using reversible logic gates AN Nagamani, HV Jayashree, HR Bhagyalakshmi Indian Journal of Computer Science and Engineering (IJCSE) 2 (4), 566-574, 2011 | 100 | 2011 |
Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder H Thapliyal, HV Jayashree, AN Nagamani, HR Arabnia Transactions on Computational Science XVII, 73-97, 2013 | 63 | 2013 |
A genetic algorithm-based heuristic method for test set generation in reversible circuits AN Nagamani, SN Anuktha, N Nanditha, VK Agrawal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 35 | 2017 |
Quaternary high performance arithmetic logic unit design AN Nagamani, S Nishchai 2011 14th Euromicro Conference on Digital System Design, 148-153, 2011 | 18 | 2011 |
Reversible radix-4 booth multiplier for DSP applications AN Nagamani, R Nikhil, M Nagaraj, VK Agrawal 2016 International Conference on Signal Processing and Communications (SPCOM …, 2016 | 17 | 2016 |
Design of optimized reversible binary adder/subtractor and BCD adder AN Nagamani, S Ashwin, VK Agrawal 2014 International Conference on Contemporary Computing and Informatics …, 2014 | 17 | 2014 |
Efficient design and FPGA implementation of JPEG encoder using verilog HDL S Sanjeevannanavar, AN Nagamani International Conference on Nanoscience, Engineering and Technology (ICONSET …, 2011 | 16 | 2011 |
An exact approach for complete test set generation of toffoli-fredkin-peres based reversible circuits AN Nagamani, S Ashwin, B Abhishek, VK Agrawal Journal of Electronic Testing 32 (2), 175-196, 2016 | 13 | 2016 |
Deterministic approach for Bridging fault detection in Peres-Fredkin and Toffoli based Reversible circuits AN Nagamani, B Abhishek, VK Agrawal 2015 IEEE International Conference on Computational Intelligence and …, 2015 | 11 | 2015 |
Modified Toffoli gate and its applications in designing components of reversible arithmetic and logic unit HV Jayashree, AN Nagamani, HR Bhagyalakshmi international journal of Advance Research in Computer Science and Software …, 2012 | 10 | 2012 |
Design of Optimized Reversible Squaring and Sum-of-Squares Units AN Nagamani, C Ramesh, VK Agrawal Circuits, Systems, and Signal Processing 37 (4), 1753-1776, 2018 | 8 | 2018 |
Design of optimized reversible binary and BCD adders AN Nagamani, S Ashwin, VK Agrawal 2015 International Conference on VLSI Systems, Architecture, Technology and …, 2015 | 8 | 2015 |
Design of Quantum Cost and Delay-Optimized Reversible Wallace Tree Multiplier Using Compressors AN Nagamani, VK Agrawal Artificial Intelligence and Evolutionary Algorithms in Engineering Systems …, 2015 | 6 | 2015 |
PES institute of Technology AN Nagamani, S Nischai Karnataka," Quaternary High Performance Arithmetic Logic Unit Design" 2011 …, 0 | 5 | |
Design of garbage free reversible multiplier for low power applications AN Nagamani, SS Kumar, VK Agrawal 2017 4th International Conference on Power, Control & Embedded Systems …, 2017 | 4 | 2017 |
Design of register file using reversible logic S Chandana, C Navya, AN Nagamani, VK Agrawal 2016 International Conference on Circuit, Power and Computing Technologies …, 2016 | 4 | 2016 |
Design of Reversible Floating Point Adder for DSP Applications AN Nagamani, CK Kavyashree, RM Saraswathy, CHV Kartika, ... Proceedings of the International Conference on Signal, Networks, Computing …, 2016 | 4 | 2016 |
Design of optimized reversible multiplier for high speed dsp application AN Nagamani, HV Prasad, RS Hathwar, VK Agrawal 2015 10th International Conference on Information, Communications and Signal …, 2015 | 4 | 2015 |
Design and analysis of esop based online testable reversible sram array AN Nagamani, VK Agrawal, RM Bhat, NK Shrilakshmi, VK Sonnad 2014 International Conference on Advances in Electronics Computers and …, 2014 | 4 | 2014 |
Design and analysis of reversible binary and BCD adders AN Nagamani, NJ Reddy, VK Agrawal Microelectronics, electromagnetics and telecommunications, 741-753, 2016 | 3 | 2016 |