| Digital image processing techniques for object detection from complex background image R Hussin, MR Juhari, NW Kang, RC Ismail, A Kamarudin Procedia Engineering 41, 340-344, 2012 | 146 | 2012 |
| An efficient modified booth multiplier architecture R Hussin, AYM Shakaff, N Idris, Z Sauli, RC Ismail, A Kamarudin 2008 International Conference on Electronic Design, 1-4, 2008 | 52 | 2008 |
| Wireless Traffic Light Controller for Emergency Vehicle through XBee and Basic Stamp Microcontroller R Hussin, RC Ismail, E Murrali, A Kamarudin Procedia Engineering 41, 636-642, 2012 | 9 | 2012 |
| 16× 16 fast signed multiplier using Booth and Vedic architecture LZ Shing, R Hussin, A Kamarudin, SN Mohyar, S Taking, MHA Aziz, ... AIP Conference Proceedings 2045 (1), 2018 | 7 | 2018 |
| Improved booth encoding for reduced area multiplier R Hussin, A Yeon, N Shakaff, N Idris, RC Ismail, A Kamarudin 2006 IEEE International Conference on Semiconductor Electronics, 773-775, 2006 | 6 | 2006 |
| Design and analysis of 32-BiT signed and unsigned multiplier using Booth, Vedic and Wallace Architecture KM Yong, R Hussin, A Kamarudin, RC Ismail, MNM Isa, SZM Naziri Journal of Physics: Conference Series 1755 (1), 012008, 2021 | 4 | 2021 |
| Redesign the 4: 2 compressor for partial product reduction R Hussin, AYM Shakaff, N Idris, Z Sauli, RC Ismail, A Kamarudin ACST’07: Proceedings of the 3rd IASTED Conference on Advances in Computer …, 2007 | 4 | 2007 |
| “LOOK & BLINK” Two Step Verification Security Log in System LK Qi, R Hussin, A Kamarudin, RC Ismail, MNM Isa, SZM Naziri Journal of Physics: Conference Series 1755 (1), 012009, 2021 | 1 | 2021 |
| Human trapped in a parked car recognition using thermal image approach SJ Cheah, R Hussin, A Kamarudin, SN Mohyar, S Taking, MHA Aziz, ... AIP conference proceedings 2045 (1), 2018 | 1 | 2018 |
| Area optimization of active reference band gap amplifier in cadence virtuoso TW Sheng, R Hussin, RC Ismail, MNM Isa, SZM Naziri, N Ahmad, MM Isa, ... AIP Conference Proceedings 2898 (1), 2024 | | 2024 |
| Development of validation process on cryptography chip using System Verilog environment L Shuang, A Kamarudin, RB Hussin AIP Conference Proceedings 2339 (1), 2021 | | 2021 |
Razaidi HussinSenior Lecturer, Universiti Malaysia Perlis在 unimap.edu.my 的电子邮件经过验证
Razaidi HussinSenior Lecturer, Universiti Malaysia Perlis在 unimap.edu.my 的电子邮件经过验证