| A 16-mW 78-dB SNDR 10-MHz BW CT ADC Using Residue-Cancelling VCO-Based Quantizer K Reddy, S Rao, R Inti, B Young, A Elshazly, M Talegaonkar, ... IEEE journal of solid-state circuits 47 (12), 2916-2927, 2012 | 228 | 2012 |
| A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer K Reddy, S Rao, R Inti, B Young, A Elshazly, M Talegaonkar, ... Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 …, 2012 | 228 | 2012 |
| Fundamental limitations of continuous-time delta–sigma modulators due to clock jitter K Reddy, S Pavan IEEE Transactions on Circuits and Systems I: Regular Papers 54 (10), 2184-2194, 2007 | 117 | 2007 |
| Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter K Reddy, S Pavan Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International …, 2006 | 117 | 2006 |
| A deterministic digital background calibration technique for VCO-based ADCs S Rao, K Reddy, B Young, PK Hanumolu IEEE Journal of Solid-State Circuits 49 (4), 950-960, 2014 | 102 | 2014 |
| A highly digital VCO-based ADC architecture for current sensing applications P Prabha, SJ Kim, K Reddy, S Rao, N Griesert, A Rao, G Winter, ... IEEE Journal of Solid-State Circuits 50 (8), 1785-1795, 2015 | 77 | 2015 |
| A 54mW 1.2 GS/s 71.5 dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS K Reddy, S Dey, S Rao, B Young, P Prabha, PK Hanumolu VLSI Circuits (VLSI Circuits), 2015 Symposium on, C256-C257, 2015 | 53 | 2015 |
| A 75dB DR 50MHz BW 3 rd order CT-ΔΣ modulator using VCO-based integrators B Young, K Reddy, S Rao, A Elshazly, T Anand, PK Hanumolu VLSI Circuits Digest of Technical Papers, 2014 Symposium on, 1-2, 2014 | 48 | 2014 |
| A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation S Dey, K Reddy, K Mayaram, TS Fiez IEEE Journal of Solid-State Circuits 53 (3), 799-813, 2018 | 37 | 2018 |
| A 20.7 mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range K Reddy, S Pavan Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, 210-213, 2008 | 35 | 2008 |
| A 4.1 mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS S Rao, K Reddy, B Young, PK Hanumolu VLSI Circuits (VLSIC), 2013 Symposium on, C68-C69, 2013 | 31 | 2013 |
| An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS M Talegaonkar, A Elshazly, K Reddy, P Prabha, T Anand, PK Hanumolu IEEE Journal of Solid-State Circuits 49 (10), 2228-2242, 2014 | 13 | 2014 |
| Transfer-function control in an active filter A Kannan, RK Guntreddi, K Reddy US Patent 8,120,417, 2012 | 12 | 2012 |
| A VCO-based current-to-digital converter for sensor applications P Prabha, SJ Kim, K Reddy, S Rao, N Griesert, A Rao, G Winter, ... Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the, 1-4, 2014 | 8 | 2014 |
| Design techniques for delta sigma modulators using VCO based ADCs K Reddy | 3 | 2014 |
| A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range K Reddy, S Pavan Analog Integrated Circuits and Signal Processing 63 (3), 397-406, 2010 | 3 | 2010 |
| A power efficient continuous time?? modulator with 15 MHz bandwidth and 70 dB dynamic range K Reddy, S Pavan Kluwer Academic Publishers, 2010 | | 2010 |
| A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation Custom Integrated Circuits Conference, 0 | | |
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