| Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE) S Agarwal, A Ghosh, PK Rana US Patent 10,103,172, 2018 | 31 | 2018 |
| Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) S Agarwal, A Ghosh, PK Rana US Patent 10,748,932, 2020 | 4 | 2020 |
| Low power integrated clock gating system and method M Berzins, L Motagi, S Agarwal US Patent 10,784,864, 2020 | 2 | 2020 |
| D flip-flops with low clock dissipation power S Agarwal, BV Sandeep, SY Kochrekar, A Ghosh, PK Rana, R Bisht US Patent App. 16/152,931, 2020 | 1 | 2020 |
| Neuroimaging evaluation of pattern of brain involvement in Japanese encephalitis and other viral encephalitis in paediatric age group SL Agarwal, M Ghosh, S Afroze, A Palit, A Ghosh, K Nayek Int J Biomed Res 9 (04), 132-136, 2018 | 1 | 2018 |
| Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) S Agarwal, A Ghosh, PK Rana US Patent 11,271,011, 2022 | | 2022 |
| Flip-flop with single pre-charge node S Agarwal, BV Sandeep, SS Jayaprakash, AK Ghosh, PK Rana US Patent 10,715,118, 2020 | | 2020 |
| Synopsys SAE based Integrated Functional Reliability Testing SM Utkarsh Garg, Shyam Agarwal, Sandeep B V SNUG-INDIA, 14, 2017 | | 2017 |
| Mri Evaluation of The Pattern of Involvement in Caries Spine With Clinical Correlation SL Agarwal, M Ghosh, A Mandal | | |
