| Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores A Cheikh, S Sordillo, A Mastrandrea, F Menichelli, G Scotti, M Olivieri IEEE Micro 41 (2), 64-71, 2021 | 30 | 2021 |
| The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes A Cheikh, G Cerutti, A Mastrandrea, F Menichelli, M Olivieri Applications in Electronics Pervading Industry, Environment and Society …, 2019 | 29 | 2019 |
| Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment M Barbirotta, A Mastrandrea, F Menichelli, F Vigli, L Blasi, A Cheikh, ... 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2020 | 20 | 2020 |
| Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores M Olivieri, A Cheikh, G Cerutti, A Mastrandrea, F Menichelli 2017 New Generation of CAS (NGCAS), 45-48, 2017 | 20 | 2017 |
| Efficient mathematical accelerator design coupled with an interleaved multi-threading RISC-V microprocessor A Cheikh, S Sordillo, A Mastrandrea, F Menichelli, M Olivieri Applications in Electronics Pervading Industry, Environment and Society …, 2020 | 19 | 2020 |
| Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri IEEE Access 10, 126074-126088, 2022 | 18 | 2022 |
| A Fault Tolerant soft-core obtained from an Interleaved-Multi-Threading RISC-V microprocessor design M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, F Vigli, M Olivieri 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021 | 15 | 2021 |
| Evaluation of dynamic triple modular redundancy in an interleaved-multi-threading risc-v core M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, M Ottavi, M Olivieri Journal of Low Power Electronics and Applications 13 (1), 2, 2022 | 14 | 2022 |
| A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled watch-dog timer L Blasi, F Vigli, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri Applications in Electronics Pervading Industry, Environment and Society …, 2020 | 13 | 2020 |
| Fault-tolerant hardware acceleration for high-performance edge-computing nodes M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, M Angioli, S Jamili, ... Electronics 12 (17), 3574, 2023 | 9 | 2023 |
| Analysis of a fault tolerant edge-computing microarchitecture exploiting vector acceleration M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri 2022 17th Conference on Ph. D Research in Microelectronics and Electronics …, 2022 | 9 | 2022 |
| Customizable vector acceleration in extreme-edge computing: a RISC-V software/hardware architecture study on VGG-16 implementation S Sordillo, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri Electronics 10 (4), 518, 2021 | 8 | 2021 |
| Improving set fault resilience by exploiting buffered DMR microarchitecture M Barbirotta, A Mastrandrea, A Cheikh, F Menichelli, M Olivieri Annual Meeting of the Italian Electronics Society, 233-238, 2022 | 4 | 2022 |
| Free flowing robot for automatic pipeline leak detection using piezoelectric film sensors S Berjaoui, R Alkhatib, A Elshiekh, M Morad, MO Diab 2015 International Mediterranean Gas and Oil Conference (MedGO), 1-3, 2015 | 3 | 2015 |
| Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme M Angioli, M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, S Jamili, ... IEEE Transactions on Computers, 2024 | 2 | 2024 |
| A RISC-V Fault-Tolerant microcontroller core architecture based on a hardware thread full-weak protection and a thread-controlled watch-dog timer L Blasi, F Vigli, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri Applications in electronics pervading industry, environment and society …, 2019 | 2 | 2019 |
| Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: an Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems M Barbirotta, F Menichelli, A Cheikh, A Mastrandrea, M Angioli, M Olivieri IEEE Access, 2024 | 1 | 2024 |
| Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor S Jamili, A Cheikh, A Mastrandrea, M Barbirotta, F Menichelli, M Angioli, ... International conference on applications in electronics pervading industry …, 2022 | 1 | 2022 |
| Contextual bandits algorithms for reconfigurable hardware accelerators M Angioli, M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, S Jamili, ... International Conference on Applications in Electronics Pervading Industry …, 2022 | 1 | 2022 |
| Exploring Variable Latency Dividers in Vector Hardware Accelerators M Angioli, M Barbirotta, A Cheikh, A Mastrandrea, M Olivieri 2024 19th Conference on Ph. D Research in Microelectronics and Electronics …, 2024 | | 2024 |
Mauro OlivieriSapienza University of Rome, Italy. - Barcelona Supercomputing Center, Spain.在 uniroma1.it 的电子邮件经过验证
Mauro OlivieriSapienza University of Rome, Italy. - Barcelona Supercomputing Center, Spain.在 uniroma1.it 的电子邮件经过验证
Antonio MastrandreaSapienza University of Rome在 uniroma1.it 的电子邮件经过验证