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Théotime Bollengier
Théotime Bollengier
Research engineer, ENSTA-Bretagne, Lab-STICC
在 ensta-bretagne.fr 的电子邮件经过验证
标题
引用次数
引用次数
年份
Extended overlay architectures for heterogeneous FPGA cluster management
M Najem, T Bollengier, JC Le Lann, L Lagadec
Journal of Systems Architecture 78, 1-14, 2017
172017
Soft timing closure for soft programmable logic cores: The argen approach
T Bollengier, L Lagadec, M Najem, JC Le Lann, P Guilloux
Applied Reconfigurable Computing: 13th International Symposium, ARC 2017 …, 2017
92017
A prototyping platform for virtual reconfigurable units
L Lagadec, JC Le Lann, T Bollengier
2014 9th International Symposium on Reconfigurable and Communication-Centric …, 2014
62014
A cost-effective approach for efficient time-sharing of reconfigurable architectures
M Najem, T Bollengier, JC Le Lann, L Lagadec
2017 International Conference on FPGA Reconfiguration for General-Purpose …, 2017
52017
Overlay architectures for heterogeneous FPGA cluster management
T Bollengier, M Najem, JC Le Lann, L Lagadec
2016 Conference on Design and Architectures for Signal and Image Processing …, 2016
52016
An integrated toolchain for overlay-centric system-on-chip
JC Le Lann, T Bollengier, M Najem, L Lagadec
2018 13th International Symposium on Reconfigurable Communication-centric …, 2018
42018
Overlay architectures for fpga resource virtualization
T Bollengier, M Najem, JC Le Lann, L Lagadec
GDR SOC SIP, 2016
42016
Zeff: Une plateforme pour l’intégration d’architectures overlay dans le cloud
T Bollengier, M Najem, JC Le Lann, L Lagadec
COMPAS 2016, 2016
22016
Live demonstration: real-time wavelet spike detection with in-vitro biological signals
A Quotb, JB Floderer, T Bollengier, R Fabre, S Renaud, Y Bornat
2012 IEEE Biomedical Circuits and Systems Conference (BioCAS), 79-79, 2012
22012
Du prototypage à l’exploitation d’overlays FPGA
T Bollengier
ENSTA Bretagne-École nationale supérieure de techniques avancées Bretagne, 2018
12018
Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC
R Milan, L Bossuet, L Lagadec, CA Lara-Nino, B Colombier, T Bollengier
IEEE Transactions on Circuits and Systems I: Regular Papers, 2024
2024
Secured-by-design systems-on-chip: a MBSE Approach
R Milan, L Lagadec, T Bollengier, L Bossuet, C Teodorov
Rapid System Prototyping, 2023
2023
Acceleration of contractor algebra on RISCV in the context of mobile robotic
P Filiol, L Jaulin, JC Le Lann, T Bollengier
Summer Workshop on Interval Methods, 2023
2023
A new interval arithmetic to generate the complementary of contractors
P Filiol, T Bollengier, L Jaulin, JC Le Lann
Summer Workshop on Interval Methods, 2022
2022
A new type of intervals for solving problems involving partially defined functions
P Filiol, T Bollgenier, L Jaulin, JC Le Lann
Gottfried Wilhelm Leibniz Universität Hannover, 2022
2022
Procédé de configuration d'un circuit logique programmable, circuit logique programmable et dispositif pour implémenter le procédé
L Lagadec, C Teodorov, JC Le Lann, T Bollengier
2022
Prototyping FPGA through overlays
T Bollengier, L Lagadec, C Teodorov
2021 IEEE International Workshop on Rapid System Prototyping (RSP), 15-21, 2021
2021
From prototyping to exploitation of FPGA overlays
T Bollengier
< bound method Organization. get_name_with_acronym of< Organization: TEL …, 2018
2018
Du prototypage à l’exploitation d’overlays FPGA| Theses. fr
T Bollengier
Brest, École nationale supérieure de techniques avancées Bretagne, 2018
2018
NEW APPROACH TO SIGNAL DETECTION IN PANCREATIC β-CELLS USING MULTI-ELECTRODE ARRAYS AND THEIR POTENTIAL USE IN BIOSENSORS
A Caro, QV Nguyen, Y Bornat, M Raoux, JB Floderer, T Bollengier, ...
DIABETES TECHNOLOGY & THERAPEUTICS 15, A56-A57, 2013
2013
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