| Compact modeling of statistical BTI under trapping/detrapping JB Velamala, KB Sutaria, H Shimizu, H Awano, T Sato, G Wirth, Y Cao IEEE transactions on electron devices 60 (11), 3645-3654, 2013 | 93 | 2013 |
| Cross-layer modeling and simulation of circuit reliability Y Cao, J Velamala, K Sutaria, MSW Chen, J Ahlbin, IS Esqueda, M Bajura, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 82 | 2013 |
| Physics matters: statistical aging prediction under trapping/detrapping JB Velamala, K Sutaria, T Sato, Y Cao Proceedings of the 49th Annual Design Automation Conference, 139-144, 2012 | 66 | 2012 |
| Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction JB Velamala, KB Sutaria, T Sato, Y Cao 2012 IEEE International Reliability Physics Symposium (IRPS), 2F. 2.1-2F. 2.5, 2012 | 56 | 2012 |
| Enhancing the reliability of STT-RAM through circuit and system level techniques Y Emre, C Yang, K Sutaria, Y Cao, C Chakrabarti 2012 IEEE Workshop on Signal Processing Systems, 125-130, 2012 | 49 | 2012 |
| Aging statistics based on trapping/detrapping: Compact modeling and silicon validation KB Sutaria, JB Velamala, CH Kim, T Sato, Y Cao IEEE Transactions on Device and Materials Reliability 14 (2), 607-615, 2014 | 33 | 2014 |
| Compact modeling of STT-MTJ devices Z Xu, C Yang, M Mao, KB Sutaria, C Chakrabarti, Y Cao Solid-State Electronics 102, 76-81, 2014 | 32 | 2014 |
| RTN in scaled transistors for on-chip random seed generation A Mohanty, KB Sutaria, H Awano, T Sato, Y Cao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 29 | 2017 |
| BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation K Sutaria, A Ramkumar, R Zhu, R Rajveev, Y Ma, Y Cao Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 26 | 2014 |
| Failure analysis of asymmetric aging under NBTI JB Velamala, KB Sutaria, VS Ravi, Y Cao IEEE Transactions on Device and Materials Reliability 13 (2), 340-349, 2012 | 23 | 2012 |
| Accelerated aging in analog and digital circuits with feedback KB Sutaria, A Mohanty, R Wang, R Huang, Y Cao IEEE Transactions on Device and Materials Reliability 15 (3), 384-393, 2015 | 22 | 2015 |
| Statistical aging under dynamic voltage scaling: A logarithmic model approach JB Velamala, K Sutaria, H Shimizu, H Awano, T Sato, Y Cao Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 21 | 2012 |
| Hierarchical modeling of phase change memory for reliable design Z Xu, KB Sutaria, C Yang, C Chakrabarti, Y Cao 2012 IEEE 30th International Conference on Computer Design (ICCD), 115-120, 2012 | 19 | 2012 |
| Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction JB Velamala, KB Sutaria, H Shimuzu, H Awano, T Sato, G Wirth, Y Cao 2013 IEEE international reliability physics symposium (IRPS), CM. 3.1-CM. 3.5, 2013 | 17 | 2013 |
| Compact modeling of STT-MTJ for SPICE simulation Z Xu, KB Sutaria, C Yang, C Chakrabarti, Y Cao 2013 Proceedings of the European Solid-State Device Research Conference …, 2013 | 16 | 2013 |
| Compact modeling of BTI for circuit reliability analysis KB Sutaria, JB Velamala, A Ramkumar, Y Cao Circuit design for reliability, 93-119, 2015 | 15 | 2015 |
| Transistor reliability characterization and modeling of the 22FFL FinFET technology CY Su, M Armstrong, L Jiang, SA Kumar, CD Landon, S Liu, I Meric, ... 2018 IEEE International Reliability Physics Symposium (IRPS), 6F. 8-1-6F. 8-7, 2018 | 12 | 2018 |
| Diagnosing bias runaway in analog/mixed signal circuits KB Sutaria, P Ren, A Ramkumar, R Zhu, X Feng, R Wang, R Huang, ... 2014 IEEE International Reliability Physics Symposium, 2D. 3.1-2D. 3.6, 2014 | 12 | 2014 |
| Modeling and simulation tools for aging effects in scaled CMOS design K Sutaria Arizona State University, 2014 | 9 | 2014 |
| Multilevel reliability simulation for IC design KB Sutaria, JB Velamala, V Ravi, G Wirth, T Sato, Y Cao Bias Temperature Instability for Devices and Circuits, 719-749, 2014 | 8 | 2014 |
Jyothi Bhaskarr Amarnadh VelamalaReliability Engineer, Intel Corporation在 intel.com 的电子邮件经过验证
Jyothi Bhaskarr Amarnadh VelamalaReliability Engineer, Intel Corporation在 intel.com 的电子邮件经过验证