| ARTEMIS: An aging-aware runtime application mapping framework for 3D NoC-based chip multiprocessors VY Raparti, N Kapadia, S Pasricha IEEE Transactions on Multi-Scale Computing Systems 3 (2), 72-85, 2017 | 44 | 2017 |
| VARSHA: Variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era N Kapadia, S Pasricha 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 42 | 2015 |
| VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip NA Kapadia, S Pasricha Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011 | 30 | 2011 |
| Process variation aware dynamic power management in multicore systems with extended range voltage/frequency scaling S Maiti, N Kapadia, S Pasricha 2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015 | 17 | 2015 |
| A power delivery network aware framework for synthesis of 3D networks-on-chip with multiple voltage islands N Kapadia, S Pasricha 2012 25th International Conference on VLSI Design, 262-267, 2012 | 17 | 2012 |
| CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era VY Raparti, N Kapadia, S Pasricha 2016 IEEE 34th International Conference on Computer Design (ICCD), 201-208, 2016 | 12 | 2016 |
| A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs N Kapadia, S Pasricha International Symposium on Quality Electronic Design (ISQED), 73-79, 2013 | 12 | 2013 |
| VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands N Kapadia, S Pasricha International Symposium on Quality Electronic Design (ISQED), 603-610, 2013 | 12 | 2013 |
| A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands N Kapadia, S Pasricha Integration 45 (3), 271-281, 2012 | 10 | 2012 |
| A system-level cosynthesis framework for power delivery and on-chip data networks in application-specific 3-D ICs N Kapadia, S Pasricha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 3-16, 2015 | 8 | 2015 |
| Process variation aware synthesis of application-specific MPSoCs to maximize yield N Kapadia, S Pasricha 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 7 | 2014 |
| Artemis: An aging-aware runtime application mapping framework for 3d noc-based chip multiprocessors N Kapadia, VY Raparti, S Pasricha Proceedings of the 9th International Symposium on Networks-on-Chip, 1-2, 2015 | 6 | 2015 |
| PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCs N Kapadia, S Pasricha 2014 IEEE 32nd International Conference on Computer Design (ICCD), 525-528, 2014 | 4 | 2014 |
| A runtime framework for robust application scheduling with adaptive parallelism in the dark-silicon era N Kapadia, S Pasricha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 534-546, 2016 | 3 | 2016 |
| Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems N Kapadia, S Pasricha The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era …, 2017 | | 2017 |
| Design-time and run-time frameworks for multi-objective optimization of 2D and 3D NoC-based multicore computing systems N Kapadia Colorado State University, 2016 | | 2016 |
| Raaed Aldujaily Rachata Ausavarungnirun Radu David Radu Stefan R Hendry, B Daya, C Fallin, D Mirzoyan, D Lee, E Cota, F Hameed, ... | | |
| Process-Variation and Soft-Error Reliability-Aware Workload Mapping with Adaptive Parallelism in SoCs N Kapadia, S Pasricha | | |
