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| Intelligent wireless power charging system L Clevenger, T Dalton, L Hsu, C Radens US Patent 8,024,012, 2011 | 287 | 2011 |
| Self-trimming method on looped patterns LA Clevenger, LLC Hsu, JA Mandelman, CJ Radens US Patent 6,632,741, 2003 | 263 | 2003 |
| Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric S Siddiqui, MP Chudzik, CJ Radens US Patent 8,373,239, 2013 | 246 | 2013 |
| Fluctuation limits & scaling opportunities for CMOS SRAM cells A Bhavnagarwala, S Kosonocky, C Radens, K Stawiasz, R Mann, Q Ye, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 212 | 2005 |
| Silicon-on-insulator vertical array device trench capacitor DRAM CJ Radens, GB Bronner, TC Chen, B Davari, JA Mandelman, D Moy, ... US Patent 6,566,177, 2003 | 193 | 2003 |
| High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ... 2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014 | 182 | 2014 |
| Method of forming a bottle-shaped trench by ion implantation K Cheng, JE Faltermeier, C Radens US Patent App. 12/187,917, 2009 | 166 | 2009 |
| Integrated chip having SRAM, DRAM and Flash memory and method for fabricating the same LL Hsu, C Radens, LK Wang US Patent 6,556,477, 2003 | 166 | 2003 |
| Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill C Radens, ME Weybright US Patent 6,190,979, 2001 | 158 | 2001 |
| A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing AJ Bhavnagarwala, S Kosonocky, C Radens, Y Chan, K Stawiasz, ... IEEE Journal of Solid-State Circuits 43 (4), 946-955, 2008 | 141 | 2008 |
| Method for hybrid DRAM cell utilizing confined strap isolation JA Mandelman, R Divakaruni, CJ Radens, S Kudelka US Patent 6,440,872, 2002 | 140 | 2002 |
| A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements H Pilo, I Arsovski, K Batson, G Braceras, J Gabric, R Houle, S Lamphier, ... IEEE Journal of Solid-State Circuits 47 (1), 97-106, 2011 | 125 | 2011 |
| Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same L Clevenger, TJ Dalton, L Hsu, C Radens, V Ramachandran, KKH Wong, ... US Patent 7,531,407, 2009 | 117 | 2009 |
| MOS transistor BB Doris, OH Dokumaci, JA Mandelman, CJ Radens US Patent 6,780,694, 2004 | 108 | 2004 |
| Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain D Chidambarrao, AC Mocuta, DM Mocuta, C Radens US Patent 7,691,698, 2010 | 100 | 2010 |
| Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof LL Hsu, CJ Radens, LK Wang US Patent 6,670,234, 2003 | 98 | 2003 |
| High performance FET with elevated source/drain region R Divakaruni, LC Hsu, RV Joshi, CJ Radens US Patent 6,864,540, 2005 | 96 | 2005 |
| Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts JH Zhang, C Radens, SJ Bentley, BA Cohen, KY Lim US Patent 9,530,866, 2016 | 92 | 2016 |
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