| Area efficient modified vedic multiplier GC Ram, YR Lakshmanna, DS Rani, KB Sindhuri 2016 International Conference on Circuit, Power and Computing Technologies …, 2016 | 67 | 2016 |
| Design of delay efficient modified 16 bit Wallace multiplier GC Ram, DS Rani, R Balasaikesava, KB Sindhuri 2016 IEEE international conference on recent trends in electronics …, 2016 | 37 | 2016 |
| Design and implementation of 32-bit adders using various full adders KAK Maurya, YR Lakshmanna, KB Sindhuri, NU Kumar 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), 1-6, 2017 | 34 | 2017 |
| Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter RBS Kesava, BL Rao, KB Sindhuri, NU Kumar 2016 conference on advances in signal processing (CASP), 248-253, 2016 | 28 | 2016 |
| Implementation of Koggestone Carry Select Adder With BEC for Efficient Area PNU B.Tapasvi,K.Bala Sindhuri,I.Chaitanya Varma IJRECE 3 (1), 2015 | 24* | 2015 |
| VLSI architecture for delay efficient 32-bit multiplier using vedic mathematic sutras GC Ram, DS Rani, R Balasaikesava, KB Sindhuri 2016 IEEE International Conference on Recent Trends in Electronics …, 2016 | 16 | 2016 |
| Area efficient vlsi architecture for square root carry select adder using zero finding logic BS Kandula, KP Vasavi, IS Prabha Procedia Computer Science 89, 640-650, 2016 | 16 | 2016 |
| Implementation and comparison of VLSI architectures of 16 bit carry select adder using Brent Kung adder NU Kumar, KB Sindhuri, KD Teja, DS Satish 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), 1-7, 2017 | 14 | 2017 |
| Artificial neural network-based secured communication strategy for vehicular ad hoc network B Sekhar, P Udayaraju, NU Kumar, KB Sinduri, B Ramakrishna, BR Babu, ... Soft Computing 27 (1), 297-309, 2023 | 9 | 2023 |
| Design of area efficient VLSI architecture for carry select adder using logic optimization technique BS Kandula, PV Kalluru, SP Inty Computational Intelligence 37 (3), 1155-1165, 2021 | 9 | 2021 |
| A systematic delay and power dominant carry save adder design AK Vamsi, NU Kumar, KB Sindhuri, GSC Teja 2018 International Conference on Smart Systems and Inventive Technology …, 2018 | 9 | 2018 |
| Implementation of regular linear carry select adder with binary to excess-1 converter KB Sindhuri International Journal of Engineering Research 4 (7), 346-350, 2015 | 4 | 2015 |
| 128-Bit Area–Efficient Carry Select Adder K BalaSindhuri, N UdayKumar, DVN Bharathi, B Tapasvi IJRASET, 0 | 4 | |
| Performance evaluation of Vedic multiplier using multiplexer-based adders N Udaya Kumar, K Bala Sindhuri, U Subbalakshmi, P Kiranmayi Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2019 | 3 | 2019 |
| Implementation of 32-bit carry select adder using Brent-Kung Adder P Nithin, NU Kumar, KB Sindhuri Indian Journal of Science and Technology 9, 44, 2016 | 3 | 2016 |
| Modified vedic multiplier using koggestone adders NUK Y. Rama Lakshmanna , G.V.S. Padma Rao , K. Bala Sindhuri IJARCCE 5 (10), 361-371, 2016 | 3* | 2016 |
| Implementation of 16-Bit Area Efficient Ling Carry Select Adder KBS P.Nithin,N.Udaya Kumar http://dx.doi.org/10.15693/ijaist/2016.v53i53.57-63 53 (53), 57-63, 2016 | 3* | 2016 |
| Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique ISP Bala Sindhuri Kandula, K.Padma Vasavi International Journal of Innovative Technology and Exploring Engineering …, 2019 | 2* | 2019 |
| Design of area and power Potent Booth multiplier using multiplexer VS Sandeep, KB Sindhuri, NU Kumar, K Rajesh 2018 3rd International Conference on Communication and Electronics Systems …, 2018 | 2 | 2018 |
| Implementation of vedic multiplier using modified architecture by routing rearrangement for high-optimization GSC Teja, KB Sindhuri, NU Kumar, AK Vamsi 2018 3rd International Conference on Communication and Electronics Systems …, 2018 | 2 | 2018 |
Rama Lakshmanna YAssociate professor在 srkrec.edu.in 的电子邮件经过验证
