3T-TFET bitcell based TFET-CMOS hybrid SRAM design for ultra-low power applications N Gupta, A Makosiej, A Vladimirescu, A Amara, C Anghel 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 361-366, 2016 | 24 | 2016 |
Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications N Gupta, A Makosiej, O Thomas, A Amara, A Vladimirescu, C Anghel 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 597-600, 2015 | 16 | 2015 |
Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS D Kumar, SK Pandey, N Gupta, H Shrimali Microelectronics Journal 95, 104666, 2020 | 12 | 2020 |
1.56 ghz/0.9 v energy-efficient reconfigurable cam/sram using 6t-cmos bitcell N Gupta, A Makosiej, A Vladimirescu, A Amara, C Anghel ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 316-319, 2017 | 12 | 2017 |
Ultra-low-power compact TFET flip-flop design for high-performance low-voltage applications N Gupta, A Makosiej, A Vladimirescu, A Amara, C Anghel 2016 17th International Symposium on Quality Electronic Design (ISQED), 107-112, 2016 | 12 | 2016 |
CMOS sensor nodes with sub-picowatt TFET memory N Gupta, A Makosiej, C Anghel, A Amara, A Vladimirescu IEEE Sensors Journal 16 (23), 8255-8262, 2016 | 11 | 2016 |
Ultra-compact SRAM design using TFETs for low power low voltage applications N Gupta, A Makosiej, A Vladimirescu, A Amara, C Anghel 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 594-597, 2016 | 11 | 2016 |
Tunnel FET based ultra-low-leakage compact 2T1C SRAM N Gupta, A Makosiej, A Vladimirescu, A Amara, C Anghel 2017 18th International Symposium on Quality Electronic Design (ISQED), 71-75, 2017 | 9 | 2017 |
A 0.4-0.9 V, 2.87 pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan M Hiienkari, N Gupta, J Teittinen, J Simonsson, M Turnquist, J Eriksson, ... 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2020 | 8 | 2020 |
Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications A Makosiej, N Gupta, N Vakul, A Vladimirescu, S Cotofana, S Mahapatra, ... Micro & Nano Letters 11 (12), 828-831, 2016 | 8 | 2016 |
Circuit for glitchless switching between asynchronous clocks VM Sharma, N Gupta US Patent 7,944,241, 2011 | 7 | 2011 |
Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM N Gupta, A Makosiej, H Shrimali, A Amara, A Vladimirescu, C Anghel IEEE Transactions on Nanotechnology 20, 270-277, 2021 | 6 | 2021 |
A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS BD Kumar, H Shrimali, N Gupta 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 6 | 2019 |
Advanced memory solutions for emerging circuits and systems B Giraud, A Makosiej, R Boumchedda, N Gupta, A Levisse, E Vianello, ... 2017 IEEE International Electron Devices Meeting (IEDM), 19.4. 1-19.4. 4, 2017 | 6 | 2017 |
TFET NDR skewed inverter based sensing method N Gupta, A Makosiej, A Vladimirescu, A Amara, S Cotofana, C Anghel 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016 | 6 | 2016 |
TFET integrated circuits: from perspective towards reality N Gupta, A Makosiej, A Amara, A Vladimirescu, C Anghel Springer, 2021 | 5 | 2021 |
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator VK Sharma, BD Kumar, MS Illikkal, JN Tripathi, N Gupta, H Shrimali 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 5 | 2019 |
Memory architecture and design methodology with adaptive read N Gupta, P Dubey, S Pathak, K Saha, A Kumar, RS KRISHNA US Patent 8,737,144, 2014 | 5 | 2014 |
Method and arrangement for ensuring valid data at a second stage of a digital register circuit N Gupta US Patent 11,558,039, 2023 | 4 | 2023 |
Refresh-free tfet memory latch N Gupta, A Amara, C Anghel, A Makosiej US Patent App. 15/916,585, 2018 | 4 | 2018 |