A 0.5-V 1.6-mW 2.4-GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28-nm CMOS N Pourmousavian, FW Kuo, T Siriburanon, M Babaie, RB Staszewski IEEE Journal of Solid-State Circuits 53 (9), 2572-2583, 2018 | 43 | 2018 |
A mismatch calibration technique for SAR ADCs based on deterministic self-calibration and stochastic quantization M Bagheri, F Schembari, N Pourmousavian, H Zare-Hoseini, D Hasko, ... IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 2883-2896, 2020 | 25 | 2020 |
A 0.5 V 1.6 mW 2.4 GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS FW Kuo, S Pourmousavian, T Siriburanon, R Chen, L Cho, CP Jou, ... 2017 Symposium on VLSI Circuits, C178-C179, 2017 | 19 | 2017 |
All-digital phase locked loop using switched capacitor voltage doubler FW Kuo, CP Jou, C Huan-Neng, LC Cho, RB Staszewski, ... US Patent 10,326,454, 2019 | 16 | 2019 |
A 180 mV 81.2%-efficient switched-capacitor voltage doubler for IoT using self-biasing deep N-well in 16-nm CMOS FinFET YT Lin, N Pourmousavian, CC Li, MS Yuan, CH Chang, RB Staszewski IEEE Solid-State Circuits Letters 1 (7), 158-161, 2018 | 10 | 2018 |
PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications FW Kuo, CP Jou, LC Cho, C Huan-Neng, RB Staszewski, ... US Patent 10,171,089, 2019 | 8 | 2019 |
All-digital phase locked loop using switched capacitor voltage doubler FW Kuo, CP Jou, C Huan-Neng, LC Cho, RB Staszewski, ... US Patent 10,862,486, 2020 | | 2020 |
Device with a high efficiency voltage multiplier YT Lin, CH Chang, MS Yuan, RB Staszewski, S Pourmousavian US Patent 10,756,083, 2020 | | 2020 |
Fully Integrated Switched-Capacitor DC-DC Converter in All-Digital PLL for IoT Applications N Pourmousavian University College Dublin. School of Electrical and Electronic Engineering, 2019 | | 2019 |
Device with a voltage multiplier YT Lin, CH Chang, MS Yuan, RB Staszewski, S Pourmousavian US Patent 10,277,117, 2019 | | 2019 |
Chapter 7: Clock Generation N Pourmousavian, T Siriburanon, FW Kuo, M Babaie, RB Staszewski Digitally Enhanced Mixed Signal Systems, 2019 | | 2019 |
ISSCC 2017 Student Research Preview [Conference Reports] A Sengupta IEEE Solid-State Circuits Magazine 9 (2), 88-90, 2017 | | 2017 |
Digital Circuits and Systems and VLSI A Stride-Based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware K Nie, W Zha, X Shi, J Li, J Xu, J Ma, M Bagheri, F Schembari, ... | | |
ISSCC AWARDS US Outphasing, M Soft-Charging | | |