| Road Identification Through Efficient Edge Segmentation Based on Morphological Operations. BMS Rani, VD Majety, CS Pittala, V Vijay, KS Sandeep, S Kiran Traitement du Signal 38 (5), 2021 | 67 | 2021 |
| ECG performance validation using operational transconductance amplifier with bias current V Vijay, CVSK Reddy, CS Pittala, RR Vallabhuni, M Saritha, M Lavanya, ... International Journal of System Assurance Engineering and Management 12 …, 2021 | 63 | 2021 |
| A Review On N-Bit Ripple-Carry Adder, Carry-Select Adder And Carry-Skip Adder V Vijay, M Sreevani, EM Rekha, K Moses, CS Pittala, KAS Shaik, ... Journal of VLSI circuits and systems 4 (01), 27-32, 2022 | 62 | 2022 |
| Universal shift register designed at low supply voltages in 20 nm FinFET using multiplexer RR Vallabhuni, J Sravana, CS Pittala, M Divya, BMS Rani, V Vijay Intelligent Sustainable Systems: Proceedings of ICISS 2021, 203-212, 2021 | 58 | 2021 |
| Numerical analysis of various plasmonic MIM/MDM slot waveguide structures CS Pittala, RR Vallabhuni, V Vijay, UR Anam, K Chaitanya International Journal of System Assurance Engineering and Management 13 (5 …, 2022 | 57 | 2022 |
| Pittala Chandra shekar, Shaik Sadulla, Putta Manoja, Rallabhandy Abhinaya, Merugu rachana, and Nakka nikhil,“ V Vijay Design and performance evaluation of energy efficient, 0 | 54 | |
| An improved GABOR wavelet transform and rough k-means clustering algorithm for MRI BRAIN tumor image segmentation CSP B. Chinna Rao, K. Raju, G. Ramesh Babu Multimedia Tools and Applications 82 (issue 18), 28143–28164, 2023 | 53* | 2023 |
| Physically unclonable functions using two-level finite state machine V Vijay, K Chaitanya, CS Pittala, SS Susmitha, J Tanusha, ... Journal of VLSI circuits and systems 4 (01), 33-41, 2022 | 48 | 2022 |
| Realization and comparative analysis of thermometer code based 4-bit encoder using 18 nm FinFET technology for analog to digital converters CS Pittala, V Parameswaran, M Srikanth, V Vijay, V Siva Nagaraju, ... Soft Computing and Signal Processing: Proceedings of 3rd ICSCSP 2020, Volume …, 2021 | 45 | 2021 |
| High speed energy efficient multiplier using 20nm FinFET technology VR Ratna, PC Shaker, S Sadulla Chandra and M, Divya and Sadulla, Shaik, High Speed Energy Efficient …, 2020 | 45 | 2020 |
| 1-Bit FinFET carry cells for low voltage high-speed digital signal processing applications CS Pittala, V Vijay, BNK Reddy Silicon 15 (2), 713-724, 2023 | 43 | 2023 |
| Grounded resistance/capacitance-controlled sinusoidal oscillators using operational transresistance amplifier S AVIRENI, CS PITTALA WSEAS Transactions on Circuits and Systems 13 (2014), 145-152, 2014 | 41 | 2014 |
| 1-Bit FinFET Carry Cells for Low Voltage High-Speed Digital Signal Processing Applications,” Silicon, 2022 CS Pittala, V Vijay, BNK Reddy | 41 | |
| Complex Filter Design for Bluetooth Receiver Application SVS Prasad, CS Pittala, V Vijay, RR Vallabhuni 2021 6th International Conference on Communication and Electronics Systems …, 2021 | 39 | 2021 |
| Universal shift register designed at low supply voltages in 15 nm CNTFET using multiplexer RR Vallabhuni, M Saritha, S Chikkapally, V Vijay, CS Pittala, S Shaik International Conference on Emerging Applications of Information Technology …, 2021 | 37 | 2021 |
| Quadrature oscillator using operational transresistance amplifier CS Pittala, A Srinivasulu 2014 International Conference on Applied Electronics, 117-120, 2014 | 37 | 2014 |
| Biasing Techniques: Validation of 3 to 8 Decoder Modules Using 18nm FinFET Nodes CS Pittala, M Lavanya, M Saritha, V Vijay, SC Venkateswarlu, ... 2021 2nd International Conference for Emerging Technology (INCET), 1-4, 2021 | 36 | 2021 |
| Energy Efficient Decoder Circuit Using Source Biasing Technique in CNTFET Technology CS Pittala, M Lavanya, V Vijay, Y Reddy, SC Venkateswarlu, ... 2021 Devices for Integrated Circuit (DevIC), 610-615, 2021 | 36 | 2021 |
| Novel methodology to validate DUTs using single access structure CS Pittala, J Sravana, G Ajitha, P Saritha, M Khadir, V Vijay, ... 2021 5th International Conference on Electronics, Materials Engineering …, 2021 | 34 | 2021 |
| Design of unbalanced ternary logic gates and arithmetic circuits V Vijay, CS Pittala, KC Koteshwaramma, AS Shaik, K Chaitanya, SG Birru, ... Journal of VLSI circuits and systems 4 (01), 20-26, 2022 | 32 | 2022 |
Prof. Avireni Srinivasulu, Ph.D. (Birla I...Dean (Research & Innovation), Mohan Babu University, Tirupati; Pro Vice-Chancellor (Ex), KRMU在 mbu.asia 的电子邮件经过验证
Prof. Avireni Srinivasulu, Ph.D. (Birla I...Dean (Research & Innovation), Mohan Babu University, Tirupati; Pro Vice-Chancellor (Ex), KRMU在 mbu.asia 的电子邮件经过验证