| Study of interconnection process for fine pitch flip chip M Lee, M Yoo, J Cho, S Lee, J Kim, C Lee, D Kang, C Zwenger, ... 2009 59th Electronic Components and Technology Conference, 720-723, 2009 | 108 | 2009 |
| Semiconductor package with increased number of input and output pins CH Lee, DC Foster, JK Choi, WJ Kim, KH Youn, SH Lee, SG Lee US Patent 6,995,459, 2006 | 107 | 2006 |
| Application of through mold via (TMV) as PoP base package J Kim, K Lee, D Park, T Hwang, K Kim, D Kang, J Kim, C Lee, C Scanlan, ... 2008 58th Electronic Components and Technology Conference, 1089-1092, 2008 | 86 | 2008 |
| Semiconductor package exhibiting efficient lead placement SG Lee, CH Lee, SH Lee US Patent 6,927,483, 2005 | 84 | 2005 |
| Semiconductor package with increased number of input and output pins CH Lee, DC Foster, JK Choi, WJ Kim, KH Youn, SH Lee, SG Lee US Patent 6,876,068, 2005 | 81 | 2005 |
| Study of FCMBGA with low CTE core substrate BY Jung, JY Gim, M Yoo, JD Kim, CH Lee, M Jimarez, N Islam, ... 2009 59th Electronic Components and Technology Conference, 301-304, 2009 | 76 | 2009 |
| Semiconductor package and method of manufacturing the same which reduces warpage YH Kim, SH Choi, CH Lee, SS Park, SS Park US Patent 7,042,072, 2006 | 70 | 2006 |
| Stacking structure for semiconductor chips and a semiconductor package using it SG Lee, YH Kim, CH Lee US Patent 6,982,485, 2006 | 62 | 2006 |
| Semiconductor package including passive elements and method of manufacture SH Lee, JY Yang, SG Lee, JH Hyun, CH Lee US Patent 6,995,448, 2006 | 61 | 2006 |
| Semiconductor device having an interposer CH Lee, KC Bae US Patent 8,183,678, 2012 | 57 | 2012 |
| Method of fabricating a semiconductor device having an interposer CH Lee, KC Bae US Patent 8,802,494, 2014 | 54 | 2014 |
| Multiple cover memory card SJ Jang, CW Park, JW Choi, JD Kim, CH Lee, CD Lee US Patent 7,359,204, 2008 | 46 | 2008 |
| Development of next generation flip chip interconnection technology using homogenized laser-assisted bonding Y Jung, D Ryu, M Gim, C Kim, Y Song, J Kim, J Yoon, C Lee 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 88-94, 2016 | 42 | 2016 |
| A study on the rheological characterization and flow modeling of molded underfill (MUF) for optimized void elimination design MW Lee, WK Jung, ES Sohn, JY Lee, CH Hwang, CH Lee 2008 58th Electronic Components and Technology Conference, 382-388, 2008 | 36 | 2008 |
| Characterization of intermetallic compound (IMC) growth in Cu wire ball bonding on Al pad metallization SH Na, TK Hwang, JS Park, JY Kim, HY Yoo, CH Lee 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 1740-1745, 2011 | 35 | 2011 |
| Below 45nm low-k layer stress minimization guide for high-performance flip-chip packages with copper pillar bumping MW Lee, JY Kim, JD Kim, CH Lee 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC …, 2010 | 32 | 2010 |
| Semiconductor device using EMC wafer support system and fabricating method thereof JY Kim, DH Park, JH Yoon, SM Seo, G Rinne, CH Lee US Patent 9,627,368, 2017 | 29 | 2017 |
| Enhanced durability memory card SJ Jang, CW Park, CH Lee US Patent 7,375,975, 2008 | 29 | 2008 |
| Development of large die fine pitch flip chip BGA using TCNCP technology Y Jung, M Lee, S Park, D Ryu, Y Jung, C Hwang, C Lee, S Park, ... 2012 IEEE 62nd Electronic Components and Technology Conference, 439-443, 2012 | 27 | 2012 |
| Molded underfill development for flipstack CSP JY Lee, KS Oh, CH Hwang, CH Lee, RDS Amand 2009 59th Electronic Components and Technology Conference, 954-959, 2009 | 25 | 2009 |
Jinseong kimQualcomm Inc在 qti.qualcomm.com 的电子邮件经过验证
