A 10-bit 500-ms/s 55-mw cmos adc A Verma, B Razavi IEEE Journal of Solid-State Circuits 44 (11), 3039-3050, 2009 | 189 | 2009 |
A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle … W Wu, CW Yao, K Godbole, R Ni, PY Chiang, Y Han, Y Zuo, A Verma, ... IEEE Journal of Solid-State Circuits 54 (5), 1254-1265, 2019 | 139 | 2019 |
A 16-channel, 28/39GHz dual-polarized 5G FR2 phased-array transceiver IC with a quad-stream IF transceiver supporting non-contiguous carrier aggregation up to 1.6 GHz BW A Verma, V Bhagavatula, A Singh, W Wu, H Nagarajan, PK Lau, X Yu, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 40 | 2022 |
Simultaneous module selection and scheduling for power-constrained testing of core based systems CP Ravikumar, G Chandra, A Verma VLSI Design 2000. Wireless and Digital Imaging in the Millennium …, 2000 | 37 | 2000 |
A polynomial-time algorithm for power constrained testing of core based systems CP Ravikumar, A Verma, G Chandra Proceedings Eighth Asian Test Symposium (ATS'99), 107-112, 1999 | 37 | 1999 |
Frequency-based measurement of mismatches between small capacitors A Verma, B Razavi IEEE Custom Integrated Circuits Conference 2006, 481-484, 2006 | 34 | 2006 |
Dual output DC-DC charge pump regulator A Verma, SM Jamal, TB Cho, S Sutardja US Patent 8,582,332, 2013 | 22 | 2013 |
Crystal oscillator with low-power mode A Verma, X Wang, S Hatanaka, SM Jamal US Patent 9,407,200, 2016 | 19 | 2016 |
Redundancy scheme for flash assisted successive approximation register (SAR) analog-to-digital converter (ADC) A Verma US Patent 9,425,814, 2016 | 16 | 2016 |
A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM W Wu, CW Yao, K Godbole, R Ni, PY Chiang, Y Han, Y Zuo, A Verma, ... 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 6403-6408, 2018 | 14 | 2018 |
A 5G FR2 power-amplifier with an integrated power-detector for closed-loop EIRP control V Bhagavatula, F Zhang, C Kuo, A Sarkar, A Verma, T Chang, X Yu, ... IEEE Journal of Solid-State Circuits 57 (5), 1257-1266, 2022 | 13 | 2022 |
A 5G FR2 (n257/n258/n261) transmitter front-end with a temperature-invariant integrated power detector for closed-loop EIRP control C Kuo, H Zhang, A Sarkar, X Yu, V Bhagavatula, A Verma, T Chang, SI Lu, ... 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 175-178, 2021 | 10 | 2021 |
Voltage regulator and method for regulating dual output voltages by selective connection between a voltage supply and multiple capacitances A Verma, SM Jamal, TB Cho, S Sutardja US Patent 9,350,234, 2016 | 9 | 2016 |
IEEE J. Solid-State Circuits A Verma, B Razavi IEEE J. Solid-State Circuits 44 (11), 3039-3050, 2009 | 7 | 2009 |
A 1.04-4V, digital-intensive dual-mode BLE 5.0/IEEE 802.15. 4 transceiver SoC with extended range in 28nm CMOS NS Kim, MG Kim, A Verma, G Seol, S Kim, S Lee, C Lo, J Han, I Jo, C Kim, ... 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 271-274, 2019 | 5 | 2019 |
A 10-Bit 500-MSs 55-roW CMOS ADC A Verma, B Razavi IEEE J. Solid-State Circuits 44 (11), 3039-3050, 2009 | 5 | 2009 |
Systems and methods for detecting local oscillator leakage and image tone in I/Q mixer based transceivers H Nagarajan, A Verma, C Lau, T Chang US Patent 10,897,228, 2021 | 3 | 2021 |
A 14-nm low-cost IF transceiver IC with low-jitter LO and flexible calibration architecture for 5G FR2 mobile applications W Wu, J Lee, PK Lau, T Kang, KK Lau, SW Yoo, X Zhao, A Verma, ISC Lu, ... 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 277-280, 2023 | 1 | 2023 |
Systems and methods for detecting local oscillator leakage and image tone in I/Q mixer based transceivers H Nagarajan, A Verma, C Lau, T Chang US Patent 11,171,609, 2021 | 1 | 2021 |
Systems and methods for detecting local oscillator leakage and image tone in I/Q mixer based transceivers H Nagarajan, A Verma, C Lau, T Chang US Patent 11,581,852, 2023 | | 2023 |