| An algorithm for synthesis of reversible logic circuits P Gupta, A Agrawal, NK Jha IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 481 | 2006 |
| Threshold network synthesis and optimization and its application to nanotechnologies R Zhang, P Gupta, L Zhong, NK Jha IEEE Transactions on computer-aided design of integrated circuits and …, 2004 | 141 | 2004 |
| Majority and minority network synthesis with application to QCA-, SET-, and TPL-based nanotechnologies R Zhang, P Gupta, NK Jha IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 79 | 2007 |
| Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies R Zhang, P Gupta, NK Jha 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 74 | 2005 |
| Synthesis and optimization of threshold logic networks with application to nanotechnologies R Zhang, P Gupta, L Zhong, NK Jha Design, Automation, and Test in Europe, 325-343, 2008 | 69 | 2008 |
| A test generation framework for quantum cellular automata circuits P Gupta, NK Jha, L Lingappan IEEE transactions on very large scale integration (VLSI) systems 15 (1), 24-36, 2007 | 63 | 2007 |
| Efficient fingerprint-based user authentication for embedded systems P Gupta, S Ravi, A Raghunathan, NK Jha Proceedings of the 42nd annual Design Automation Conference, 244-247, 2005 | 62 | 2005 |
| Hardware-software codesign P Gupta IEEE Potentials 20 (5), 31-32, 2002 | 40 | 2002 |
| A physical design tool for carbon nanotube field-effect transistor circuits J Huang, M Zhu, S Yang, P Gupta, W Zhang, SM Rubin, G Garretón, J He ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (3), 25, 2012 | 30 | 2012 |
| A CAD tool for design and analysis of CNFET circuits J Huang, M Zhu, P Gupta, S Yang, SM Rubin, G Garret, J He 2010 IEEE International Conference of Electron Devices and Solid-State …, 2010 | 25 | 2010 |
| A high-level interconnect power model for design space exploration P Gupta, L Zhong, NK Jha Proceedings of the 2003 IEEE/ACM international conference on Computer-aided …, 2003 | 25 | 2003 |
| An algorithm for nanopipelining of RTD-based circuits and architectures P Gupta, NK Jha IEEE transactions on nanotechnology 4 (2), 159-167, 2005 | 24 | 2005 |
| Testing of clock-domain crossing faults in multi-core system-on-chip N Karimi, Z Kong, K Chakrabarty, P Gupta, S Patil 2011 Asian Test Symposium, 7-14, 2011 | 19 | 2011 |
| Test generation for combinational quantum cellular automata (QCA) circuits P Gupta, NK Jha, L Lingappan Proceedings of the conference on Design, automation and test in Europe …, 2006 | 19 | 2006 |
| Automatic test generation for combinational threshold logic networks P Gupta, R Zhang, NK Jha IEEE transactions on very large scale integration (VLSI) systems 16 (8 …, 2008 | 16 | 2008 |
| An automatic test pattern generation framework for combinational threshold logic networks P Gupta, R Zhang, NK Jha IEEE International Conference on Computer Design: VLSI in Computers and …, 2004 | 16 | 2004 |
| Power analysis attack resistance engineering by dynamic voltage and frequency scaling S Yang, P Gupta, M Wolf, D Serpanos, V Narayanan, Y Xie ACM Transactions on Embedded Computing Systems (TECS) 11 (3), 62, 2012 | 15 | 2012 |
| An Algorithm for Nano-pipelining of Circuits and Architectures for a Nanotechnology P Gupta, NK Jha Proceedings of the conference on Design, automation and test in Europe …, 2004 | 15 | 2004 |
| Test generation for clock-domain crossing faults in integrated circuits N Karimi, K Chakrabarty, P Gupta, S Patil 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 406-411, 2012 | 12 | 2012 |
| NBTI-aware circuit node criticality computation S Yang, W Wang, M Hagan, W Zhang, P Gupta, Y Cao ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (3), 23, 2013 | 9 | 2013 |
