Efficient Hardware Implementation of Decision Tree Training Accelerator R Choudhury, SR Ahamed, P Guha SN Computer Science 2 (5), 1-10, 2021 | 6 | 2021 |
Design and implementation of mixed parallel and dataflow architecture for intra-prediction hardware in hevc decoder R Choudhury, P Rangababu International Symposium on VLSI Design and Test, 742-750, 2017 | 5 | 2017 |
FPGA Implementation of Low Complexity Hybrid Decision Tree Training Accelerator R Choudhury, SR Ahamed, P Guha IEEE International Midwest Symposium on Circuits and Systems, August 2021, 2021 | 4 | 2021 |
Training accelerator for two means decision tree R Choudhury, SR Ahamed, P Guha IEEE Transactions on Very Large Scale Integration, 2021 | 4 | 2021 |
Pipelined training accelerator for portable devices R Choudhury, SR Ahamed, P Guha AEU-International Journal of Electronics and Communications 177, 155167, 2024 | 1 | 2024 |
FPGA implementation of batch-mode depth-pipelined two means decision tree R Choudhury, SR Ahamed, P Guha IEEE Embedded Systems Letters 15 (1), 17-20, 2022 | 1 | 2022 |
Hardware Implementation of Low Complexity High-speed Perceptron Block R Choudhury, SR Ahamed, P Guha 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 26-30, 2022 | 1 | 2022 |
Simplified Oblique Decision Tree Accelerator R Choudhury, SR Ahamed, P Guha IEEE Embedded Systems Letters, 2024 | | 2024 |
Efficient Hardware Implementation of Decision Tree Training Accelerator R Choudhury, SR Ahamed, P Guha 2020 6th IEEE International Symposium on Smart Electronic Systems (IEEE-iSES), 2020 | | 2020 |