Spintronic processing unit in spin transfer torque magnetic random access memory H Zhang, W Kang, K Cao, B Wu, Y Zhang, W Zhao IEEE Transactions on Electron Devices 66 (4), 2017-2022, 2019 | 54 | 2019 |
Temperature impact analysis and access reliability enhancement for 1T1MTJ STT-RAM B Wu, Y Cheng, J Yang, A Todri-Sanial, W Zhao IEEE Transactions on Reliability 65 (4), 1755-1768, 2016 | 49 | 2016 |
Ultra-dense ring-shaped racetrack memory cache design G Wang, Y Zhang, B Zhang, B Wu, J Nan, X Zhang, Z Zhang, JO Klein, ... IEEE Transactions on Circuits and Systems I: Regular Papers 66 (1), 215-225, 2018 | 40 | 2018 |
Field-free spin–orbit-torque switching of perpendicular magnetization aided by uniaxial shape anisotropy Z Wang, Z Li, M Wang, B Wu, D Zhu, W Zhao Nanotechnology 30 (37), 375202, 2019 | 37 | 2019 |
Spintronic processing unit within voltage-gated spin Hall effect MRAMs H Zhang, W Kang, B Wu, P Ouyang, E Deng, Y Zhang, W Zhao IEEE Transactions on Nanotechnology 18, 473-483, 2019 | 27 | 2019 |
Field-free 3T2SOT MRAM for non-volatile cache memories B Wu, C Wang, Z Wang, Y Wang, D Zhang, D Liu, Y Zhang, XS Hu IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4660-4669, 2020 | 22 | 2020 |
A comparative cross-layer study on racetrack memories: Domain wall vs skyrmion W Kang, B Wu, X Chen, D Zhu, Z Wang, X Zhang, Y Zhou, Y Zhang, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 16 (1), 1-17, 2019 | 22 | 2019 |
Write-efficient STT/SOT hybrid triple-level cell for high-density MRAM Y Xu, B Wu, Z Wang, Y Wang, Y Zhang, W Zhao IEEE Transactions on Electron Devices 67 (4), 1460-1465, 2020 | 20 | 2020 |
An adaptive 3T-3MTJ memory cell design for STT-MRAM-based LLCs L Xue, B Wu, B Zhang, Y Cheng, P Wang, C Park, J Kan, SH Kang, Y Xie IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 484-495, 2018 | 20 | 2018 |
Novel radiation hardening read/write circuits using feedback connections for spin–orbit torque magnetic random access memory B Wang, Z Wang, B Wu, Y Bai, K Cao, Y Zhao, Y Zhang, W Zhao IEEE Transactions on Circuits and Systems I: Regular Papers 66 (5), 1853-1862, 2019 | 19 | 2019 |
Evaluation of ultrahigh-speed magnetic memories using field-free spin–orbit torque Z Wang, B Wu, Z Li, X Lin, J Yang, Y Zhang, W Zhao IEEE Transactions on Magnetics 54 (11), 1-5, 2018 | 14 | 2018 |
An adaptive thermal-aware ECC scheme for reliable STT-MRAM LLC design B Wu, B Zhang, Y Cheng, Y Wang, D Liu, W Zhao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (8 …, 2019 | 13 | 2019 |
A survey of MRAM-centric computing: From near memory to in memory Y Li, T Bai, X Xu, Y Zhang, B Wu, H Cai, B Pan, W Zhao IEEE Transactions on Emerging Topics in Computing 11 (2), 318-330, 2022 | 11 | 2022 |
An energy efficient accelerator for bidirectional recurrent neural networks (BiRNNs) using hybrid-iterative compression with error sensitivity G Nan, Z Wang, C Wang, B Wu, Z Wang, W Liu, F Lombardi IEEE Transactions on Circuits and Systems I: Regular Papers 68 (9), 3707-3718, 2021 | 10 | 2021 |
A novel high performance and energy efficient NUCA architecture for STT-MRAM LLCs with thermal consideration B Wu, P Dai, Y Cheng, Y Wang, J Yang, Z Wang, D Liu, W Zhao IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 10 | 2019 |
A NAND-SPIN-Based Magnetic ADC B Wu, Z Wang, Y Li, Y Wang, D Liu, W Zhao, XS Hu IEEE Transactions on Circuits and Systems II: Express Briefs 68 (2), 617-621, 2020 | 9 | 2020 |
PDS: Pseudo-differential sensing scheme for STT-MRAM W Kang, T Pang, B Wu, W Lv, Y Zhang, G Sun, W Zhao Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 9 | 2016 |
MLiM: High-performance magnetic logic in-memory scheme with unipolar switching SOT-MRAM B Wu, H Zhu, K Chen, C Yan, W Liu IEEE Transactions on Circuits and Systems I: Regular Papers 70 (6), 2412-2424, 2023 | 8 | 2023 |
Design and Optimization of an Area-efficient SOT-MRAM C Wang, Z Wang, B Wu, W Zhao 2019 IEEE International Conference on Electron Devices and Solid-State …, 2019 | 7 | 2019 |
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM B Wu, Y Cheng, Y Wang, A Todri-Sanial, G Sun, L Torres, W Zhao Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015 | 7 | 2015 |