| Fast ECO leakage optimization using graph convolutional network W Lee, Y Kwon, Y Shin Proceedings of the 2020 on Great Lakes Symposium on VLSI, 187-192, 2020 | 6 | 2020 |
| Integrated power distribution network synthesis for mixed macro blocks and standard cells D Hyun, W Lee, J Park, Y Shin IEEE Transactions on Circuits and Systems II: Express Briefs 70 (6), 2211-2215, 2023 | 4 | 2023 |
| Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic S Lee, W Lee, Y Shin Proceedings of the Great Lakes Symposium on VLSI 2024, 38-43, 2024 | 1 | 2024 |
| Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage Y Song, G Cho, W Lee, Y Shin 2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 1-6, 2023 | | 2023 |
| Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting W Lee, I Cho, G Cho, Y Shin 2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 1-6, 2023 | | 2023 |
