Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip D Lee, S Das, JR Doppa, PP Pande, K Chakrabarty ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (5 …, 2018 | 47 | 2018 |
Small-world network enabled energy efficient and robust 3D NoC architectures S Das, D Lee, DH Kim, PP Pande Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 133-138, 2015 | 20 | 2015 |
Impact of electrostatic coupling on monolithic 3D-enabled network on chip D Lee, S Das, JR Doppa, PP Pande, K Chakrabarty ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (6 …, 2019 | 18 | 2019 |
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture D Lee, S Das, PP Pande Integration the VLSI Journal 65 (March 2019), 282-292, 2018 | 13 | 2018 |
Design space exploration of 3D network-on-chip: A sensitivity-based optimization approach D Lee, S Das, DH Kim, JR Doppa, PP Pande ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (3), 1-26, 2018 | 5 | 2018 |
VFI-based power management to enhance the lifetime of high-performance 3D NoCs S Das, D Lee, W Choi, JR Doppa, PP Pande, K Chakrabarty ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (1 …, 2017 | 4 | 2017 |
Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture D Lee, S Das, PP Pande 2017 18th International Symposium on Quality Electronic Design (ISQED), 271-276, 2017 | 3 | 2017 |
Exploring Power-Thermal-Performance Trade-Offs in 3D Network on Chip-Enabled Many-Core Systems D Lee Washington State University, 2018 | | 2018 |