| Analysis and design of resilient VLSI circuits: mitigating soft errors and process variations R Garg Springer Science & Business Media, 2009 | 96 | 2009 |
| A design approach for radiation-hard digital electronics R Garg, N Jayakumar, SP Khatri, G Choi Proceedings of the 43rd annual Design Automation Conference, 773-778, 2006 | 84 | 2006 |
| A fast, analytical estimator for the SEU-induced pulse width in combinational designs R Garg, C Nagpal, SP Khatri Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 918-923, 2008 | 48 | 2008 |
| A delay-efficient radiation-hard digital design approach using CWSP elements C Nagpal, R Garg, SP Khatri Proceedings of the conference on Design, automation and test in Europe, 354-359, 2008 | 43 | 2008 |
| Circuit-level design approaches for radiation-hard digital electronics R Garg, N Jayakumar, SP Khatri, GS Choi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (6), 781-792, 2009 | 38 | 2009 |
| A novel, highly SEU tolerant digital circuit design approach R Garg, SP Khatri Computer Design, 2008. ICCD 2008. IEEE International Conference on, 14-20, 2008 | 32 | 2008 |
| A robust pulsed flip-flop and its use in enhanced scan design R Kumar, KC Bollapalli, R Garg, T Soni, SP Khatri Computer Design, 2009. ICCD 2009. IEEE International Conference on, 97-102, 2009 | 29 | 2009 |
| A PLA based asynchronous micropipelining approach for subthreshold circuit design N Jayakumar, R Garg, B Gamache, SP Khatri Proceedings of the 43rd annual Design Automation Conference, 419-424, 2006 | 28 | 2006 |
| A radiation tolerant phase locked loop design for digital electronics R Kumar, V Karkala, R Garg, T Jindal, SP Khatri Computer Design, 2009. ICCD 2009. IEEE International Conference on, 505-510, 2009 | 27 | 2009 |
| A single-supply true voltage level shifter R Garg, G Mallarapu, SP Khatri Proceedings of the conference on Design, automation and test in Europe, 979-984, 2008 | 23 | 2008 |
| A robust, fast pulsed flip-flop design A Venkatraman, R Garg, SP Khatri Proceedings of the 18th ACM Great Lakes symposium on VLSI, 119-122, 2008 | 21 | 2008 |
| 3D simulation and analysis of the radiation tolerance of voltage scaled digital circuits R Garg, SP Khatri Analysis and Design of Resilient VLSI Circuits, 71-86, 2010 | 20 | 2010 |
| 3d simulation and analysis of the radiation tolerance of voltage scaled digital circuit R Garg, SP Khatri Computer Design, 2009. ICCD 2009. IEEE International Conference on, 498-504, 2009 | 20 | 2009 |
| CMOS comparators for high-speed and low-power applications ER Menendez, DK Maduike, R Garg, SP Khatri Computer Design, 2006. ICCD 2006. International Conference on, 76-81, 2007 | 20 | 2007 |
| Polymeric sensors to monitor cockroach locomotion H Lee, R Cooper, B Mika, D Clayton, R Garg, JM Gonzalez, SB Vinson, ... IEEE Sensors Journal 7 (12), 1698-1702, 2007 | 17 | 2007 |
| SEU hardened clock regeneration circuits R Dash, R Garg, SP Khatri, G Choi Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design …, 2009 | 16 | 2009 |
| A lithography-friendly structured ASIC design approach S Gopalani, R Garg, SP Khatri, M Cheng Proceedings of the 18th ACM Great Lakes symposium on VLSI, 315-320, 2008 | 16 | 2008 |
| Minimizing and exploiting leakage in VLSI design N Jayakumar, S Paul, R Garg Springer Science & Business Media, 2009 | 14 | 2009 |
| A PLL design based on a standing wave resonant oscillator V Karkala, KC Bollapalli, R Garg, SP Khatri Computer Design, 2009. ICCD 2009. IEEE International Conference on, 511-516, 2009 | 14 | 2009 |
| Modeling dynamic stability of SRAMs in the presence of single event upsets (SEUs) R Garg, P Li, SP Khatri Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on …, 2008 | 14 | 2008 |
