Technology computer aided design C Sarkar CRC Press, 2018 | 51 | 2018 |
Influence of Underlap on Gate Stack DG-MOSFET for analytical study of Analog/RF performance A Kundu, A Dasgupta, R Das, S Chakraborty, A Dutta, CK Sarkar Superlattices and Microstructures 94, 60-73, 2016 | 47 | 2016 |
Handbook for III-V high electron mobility transistor technologies D Nirmal, J Ajayan CRC Press, 2019 | 39 | 2019 |
Nanotechnology: synthesis to applications S Roy, CK Ghosh, CK Sarkar CRC Press, 2017 | 37 | 2017 |
Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions K Koley, B Syamal, A Kundu, N Mohankumar, CK Sarkar Microelectronics Reliability 52 (11), 2572-2578, 2012 | 35 | 2012 |
Comparative Study of Variations in Gate Oxide Material of a Novel Underlap DG MOS-HEMT for Analog/RF and High Power Applications A Mondal, A Roy, R Mitra, A Kundu Silicon, 1-7, 2019 | 30 | 2019 |
Analytical modeling of label free biosensor using charge plasma based gate underlap dielectric modulated MOSFET CKS Manash Chanda, Rahul Das, Atanu Kundu Superlattices and Microstructures 104, 451-460, 2017 | 29 | 2017 |
Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET A Kundu, K Koley, A Dutta, CK Sarkar Microelectronics Reliability 54 (12), 2717-2722, 2014 | 29 | 2014 |
Influence of channel thickness on analog and RF performance enhancement of an underlap DG AlGaN/GaN based MOS-HEMT device A Roy, R Mitra, A Kundu 2019 Devices for Integrated Circuit (DevIC), 186-190, 2019 | 18 | 2019 |
Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture R Das, S Chakraborty, A Dasgupta, A Dutta, A Kundu, CK Sarkar Superlattices and Microstructures 97, 386-396, 2016 | 17 | 2016 |
Comparisons between dual and tri material gate on a 32 nm double gate MOSFET A Dasgupta, R Das, S Chakraborty, A Dutta, A Kundu, CK Sarkar Nano 11 (10), 1650117, 2016 | 15 | 2016 |
Two-dimensional modeling of the underlap graded-channel FinFET A Chattopadhyay, A Kundu, CK Sarkar, C Bose Journal of Computational Electronics 19, 688-699, 2020 | 11 | 2020 |
A comparative analysis of analog performances of underlapped dual gate AlGaN/GaN based MOS-HEMT and Schottky-HEMT H Mukherjee, R Dasgupta, M Kar, A Kundu 2020 IEEE Calcutta Conference (CALCON), 412-416, 2020 | 10 | 2020 |
Impact of lateral straggle on the analog/RF performance of asymmetric gate stack double gate MOSFET GS Sivaram, S Chakraborty, R Das, A Dasgupta, A Kundu, CK Sarkar Superlattices and Microstructures 97, 477-488, 2016 | 10 | 2016 |
RF parameter extraction of Bulk FinFET: A non quasi static approach A Kundu, B Syamal, K Koley, CK Sarkar, N Mohankumar 2010 IEEE International Conference of Electron Devices and Solid-State …, 2010 | 10 | 2010 |
Analog/RF and power performance analysis of an underlap DG AlGaN/GaN based high-K dielectric MOS-HEMT A Roy, R Mitra, A Mondal, A Kundu Silicon 14 (5), 2211-2218, 2022 | 8 | 2022 |
Enhancement in analog/RF and power performance of underlapped dual-gate GaN-based MOSHEMTs with quaternary InAlGaN barrier of varying widths H Mukherjee, M Kar, A Kundu Journal of Electronic Materials, 1-12, 2022 | 7 | 2022 |
Memoryless nonlinearity in IT JL FinFET with spacer technology: Investigation towards reliability B Vandana, SK Mohapatra, JK Das, KP Pradhan, A Kundu, BK Kaushik Microelectronics Reliability 119, 114072, 2021 | 7 | 2021 |
A linearity based comparison between symmetric and asymmetric lateral diffusion for a 22 nm Underlapped DG-MOSFET A Chattopadhyay, R Das, A Dasgupta, A Kundu, CK Sarkar Superlattices and Microstructures 107, 69-82, 2017 | 7 | 2017 |
Effect of spacer dielectric engineering on asymmetric source underlapped double gate MOSFET using gate stack A Chattopadhyay, A Dasgupta, R Das, A Kundu, CK Sarkar Superlattices and Microstructures 101, 87-95, 2017 | 7 | 2017 |