| 2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure S Kumar, E Goel, K Singh, B Singh, PK Singh, K Baral, S Jit IEEE Transactions on Electron Devices 64 (3), 960-968, 2017 | 172 | 2017 |
| Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications MR Tripathy, AK Singh, A Samad, S Chander, K Baral, PK Singh, S Jit IEEE Transactions on Electron Devices 67 (3), 1285-1292, 2020 | 110 | 2020 |
| 2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure S Kumar, K Singh, S Chander, E Goel, PK Singh, K Baral, B Singh, S Jit IEEE Transactions on Electron Devices 65 (1), 331-338, 2017 | 68 | 2017 |
| Temperature analysis of Ge/Si heterojunction SOI-tunnel FET S Chander, SK Sinha, S Kumar, PK Singh, K Baral, K Singh, S Jit Superlattices and Microstructures 110, 162-170, 2017 | 60 | 2017 |
| III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications MR Tripathy, AK Singh, K Baral, PK Singh, S Jit Superlattices and Microstructures 142, 106494, 2020 | 49 | 2020 |
| Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs S Chander, S Baishya, SK Sinha, S Kumar, PK Singh, K Baral, ... Superlattices and Microstructures 131, 30-39, 2019 | 39 | 2019 |
| Simulation study and comparative analysis of some TFET structures with a novel partial-ground-plane (PGP) based TFET on SELBOX structure AK Singh, MR Tripathy, S Chander, K Baral, PK Singh, S Jit Silicon 12, 2345-2354, 2020 | 30 | 2020 |
| Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): introduction to a BG-HJ-STEFT based CMOS inverter AK Singh, MR Tripathy, K Baral, PK Singh, S Jit Microelectronics journal 102, 104775, 2020 | 27 | 2020 |
| Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET MR Tripathy, AK Singh, A Samad, PK Singh, K Baral, S Jit Semiconductor Science and Technology 35 (10), 105014, 2020 | 26 | 2020 |
| Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate AK Singh, MR Tripathy, K Baral, PK Singh, S Jit Applied Physics A 126 (9), 681, 2020 | 21 | 2020 |
| Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked … MR Tripathy, A Samad, AK Singh, PK Singh, K Baral, AK Mishra, S Jit Microelectronics Reliability 119, 114073, 2021 | 20 | 2021 |
| Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis PK Singh, K Baral, S Kumar, S Chander, MR Tripathy, AK Singh, S Jit Applied Physics A 126, 1-11, 2020 | 17 | 2020 |
| GaSb/GaAs Type-II heterojunction TFET on SELBOX Substrate for dielectric modulated label-free biosensing application AK Singh, MR Tripathy, K Baral, S Jit IEEE Transactions on Electron Devices 69 (9), 5185-5192, 2022 | 15 | 2022 |
| Deep insight into DC/RF and linearity parameters of a novel back gated ferroelectric TFET on SELBOX substrate for ultra low power applications AK Singh, MR Tripathy, PK Singh, K Baral, S Chander, S Jit Silicon 13, 3853-3863, 2021 | 13 | 2021 |
| 2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET K Baral, PK Singh, S Kumar, A Singh, M Tripathy, S Chander, S Jit AEU-International Journal of Electronics and Communications 116, 153071, 2020 | 12 | 2020 |
| Performance optimization of ZnO nanorods ETL based hybrid perovskite solar cells with different seed layers DK Jarwal, AK Mishra, K Baral, A Kumar, C Kumar, G Rawat, B Mukherjee, ... IEEE Transactions on Electron Devices 69 (5), 2494-2499, 2022 | 11 | 2022 |
| Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge PK Singh, K Baral, S Kumar, S Chander, S Jit Indian Journal of physics 94, 841-849, 2020 | 11 | 2020 |
| Performance comparison of Ge/Si hetero-junction vertical tunnel FET with and without gate-drain underlapped structure with application to digital inverter MR Tripathy, AK Singh, A Samad, K Baral, PK Singh, S Jit 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020 | 10 | 2020 |
| Comparative analysis and performance optimization of low-cost solution-processed hybrid perovskite-based solar cells with different organic HTLs DK Jarwal, C Dubey, K Baral, A Bera, G Rawat IEEE Transactions on Electron Devices 69 (9), 5012-5020, 2022 | 9 | 2022 |
| Ultrathin body nanowire hetero-dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability K Baral, PK Singh, S Kumar, S Chander, S Jit Superlattices and Microstructures 138, 106364, 2020 | 9 | 2020 |
Satyabrata JitIndian Institute of Technology (Banaras Hindu University) Varanasi, India在 iitbhu.ac.in 的电子邮件经过验证
