Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling M Debnath, D Konstantinou, C Nicopoulos, G Dimitrakopoulos, WM Lin, ... Proceedings of the 2nd International Workshop on Advanced Interconnect …, 2017 | 16 | 2017 |
Hardware-based online self-diagnosis for faulty device identification in large-scale IoT systems J Lee, M Debnath, A Patki, M Hasan, C Nicopoulos 2018 IEEE/ACM Third International Conference on Internet-of-Things Design …, 2018 | 7 | 2018 |
Prioritized out-of-order instruction dispatching techniques for Simultaneous Multi-Threading (SMT) processors M Debnath, B Lee, WM Lin WIP session of 30th IEEE real-time systems symposium (RTSS), 2009 | 6 | 2009 |
LAWC: Optimizing write cache using layout-aware I/O scheduling for all flash storage K Ganesh, Y Kim, M Debnath, S Park, J Lee IEEE Transactions on Computers 66 (11), 1890-1902, 2017 | 5 | 2017 |
Exploiting Reuse-Frequency with Speculative and Dynamic Updates in an Enhanced Directory Based Coherence Protocol N Ferdous, M Debnath, BK Lee, E John Proceedings of the International Conference on Parallel and Distributed …, 2014 | 2 | 2014 |
Adaptive instruction dispatching techniques for Simultaneous Multi-Threading (SMT) processors M Debnath, WM Lin, E John Computers & Electrical Engineering 38 (6), 1616-1626, 2012 | 1 | 2012 |
Composite pseudo associative cache with victim cache for mobile processors LD Bobbala, M Debnath, BK Lee The University of Texas at San Antonio, 2010 | 1 | 2010 |
Low-Cost Congestion Management for NOC M Debnath, J Lee | | 2019 |
Instruction Dispatching Techniques for SMT Processors: Efficient Instruction Queue sharing for SMT Processors M Debnath, WM Lin | | 2017 |
A Study on Performance Impact of Network Delay in Chip Multi Processors M Debnath, A Patel, BK Lee Workshop on Unique Chips and Systems UCAS-7, 4, 2012 | | 2012 |
Welcome to ICCD 2011! G Gaydadjiev, S Tahar, G Byrd, K Schneider 2011 IEEE 29th International Conference on Computer Design (ICCD), IX-XIX, 2011 | | 2011 |