| 14.1 A 2.9 TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems G Desoli, N Chawla, T Boesch, S Singh, E Guidetti, F De Ambroggi, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 238-239, 2017 | 171 | 2017 |
| Configurable accelerator framework including a stream switch having a plurality of unidirectional stream links T Boesch, G Desoli US Patent 11,562,115, 2023 | 124 | 2023 |
| Multi-portal bridge for providing network connectivity T Thaler, G Dickmann, T Boesch, C Heidelberger, M Stadler, M Dasen US Patent 6,772,267, 2004 | 90 | 2004 |
| Deep convolutional network heterogeneous architecture G Desoli, T Boesch, N Chawla, SP Singh, E Guidetti, FG De Ambroggi, ... US Patent 12,118,451, 2024 | 57 | 2024 |
| Acceleration unit for a deep learning engine SP Singh, T Boesch, G Desoli US Patent 11,687,762, 2023 | 57 | 2023 |
| Arithmetic unit for deep learning acceleration SP Singh, G Desoli, T Boesch US Patent 11,586,907, 2023 | 51 | 2023 |
| Hardware accelerator engine T Boesch, G Desoli US Patent 12,073,308, 2024 | 50 | 2024 |
| Reconfigurable interconnect T Boesch, G Desoli US Patent 10,402,527, 2019 | 33 | 2019 |
| 16.7 A 40-310TOPS/W SRAM-based all-digital up to 4b in-memory computing multi-tiled NN accelerator in FD-SOI 18nm for deep-learning edge applications G Desoli, N Chawla, T Boesch, M Avodhyawasi, H Rawat, H Chawla, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 260-262, 2023 | 23 | 2023 |
| Frame buffer-less stream processor for accurate real-time interest point detection GD Licciardo, T Boesch, D Pau, L Di Benedetto Integration 54, 10-23, 2016 | 23 | 2016 |
| Reconfigurable interconnect T Boesch, G Desoli US Patent 11,227,086, 2022 | 21 | 2022 |
| Tool to create a reconfigurable interconnect framework T Boesch, G Desoli US Patent 10,417,364, 2019 | 17 | 2019 |
| Tool to create a reconfigurable interconnect framework T Boesch, G Desoli US Patent 11,675,943, 2023 | 16 | 2023 |
| Hardware accelerator method, system and device M Rossi, G Desoli, T Boesch, C Cappetta US Patent 11,442,700, 2022 | 15 | 2022 |
| Convolutional network hardware accelerator device, system and method G Desoli, T Boesch, C Cappetta, UM Iannuzzi US Patent 11,740,870, 2023 | 10 | 2023 |
| Convolution acceleration with embedded vector decompression T Boesch, G Desoli, SP Singh, C Cappetta US Patent 11,531,873, 2022 | 9 | 2022 |
| Design space exploration for orlando ultra low-power convolutional neural network soc A Erdem, C Silvano, T Boesch, A Ornstein, SP Singh, G Desoli 2018 IEEE 29th International Conference on Application-specific Systems …, 2018 | 8 | 2018 |
| Tagged memory operated at lower vmin in error tolerant system N Chawla, G Desoli, A Grover, T Boesch, SP Singh, M Ayodhyawasi US Patent 11,360,667, 2022 | 7 | 2022 |
| Runtime design space exploration and mapping of dcnns for the ultra-low-power orlando soc A Erdem, C Silvano, T Boesch, AC Ornstein, SP Singh, G Desoli ACM Transactions on Architecture and Code Optimization (TACO) 17 (2), 1-25, 2020 | 7 | 2020 |
| 14.1 a 2.9 tops/w deep convolutional neural network soc in fd-soi 28nm for intelligent embedded systems, in 2017 IEEE International Solid-State Circuits Conference (ISSCC) G Desoli, N Chawla, T Boesch, S Singh, E Guidetti, F De Ambroggi, ... IEEE, 2017 | 7 | 2017 |
