| High-Speed Vedic Multiplier Implementation Using Memristive and Speculative Adders B Ande, LD Kalidindi, PK Mallula, PV Dantuluri, N Vegesna 2022 International Conference on Computing, Communication and Power …, 2022 | 2 | 2022 |
| Guarded Low Power Hardware Implementations A Bhargav, MMA Basiri 2023 IEEE 7th Conference on Information and Communication Technology (CICT), 1-5, 2023 | 1 | 2023 |
| DESIGN OF EFFICIENT MULTI BITS ERROR CORRECTION CODES USING OLS CODES RAM TALAGALLA,TULASI, M VIJAYARAMARAJU, A BHARGAV Journal of Emerging Technologies and Innovative Research (JETIR) 7 (8), 784-791, 2020 | | 2020 |
| Modified Carry Skip BCD Adder using Reversible Logic Gates A Bhargav, CHN SrinivasaRao, D Bhavani International Journal of Management, Technology And Engineering 9 (8), 500 - 504, 2019 | | 2019 |
| Error correction codes derived from orthogonal Latin square codes A Bhargav, Y Varthamanan International Journal of Recent Technology and Engineering 8 (2S8), 1948-1952, 2019 | | 2019 |
| Analysis of High Speed Array Multipliers Using Multiplexers AB Ch.Naga srinivas IJMTST 4 (4), 211-215, 2018 | | 2018 |
| DESIGN OF ALU USING REVERSIBLE GATES AND VECTORED LOGIC AB 1N.L.TEJASWI, 2P.ANJALI, 3P.SRIKANTH, 4K.VIKRAM RAJA Proceedings of International Conference on Science, Technology, Engineering …, 2017 | | 2017 |
| a novel architecture for less complexity design based non redundant radix-4 signed multipliers BS A.BHARGAV, A.BHOGESWARARAO, J.E.N.ABHILASH ICEMRCI, 331- 341, 2016 | | 2016 |
| A Novel Implementation of CRC Algorithm In XMODEM Protocol on FPGA Using VHDL A Bhargav IJECER 1 (6), 8-12, 2013 | | 2013 |
Kalidindi Lakshmi DivyaAssistant Professor of ECE,SRKR在 srkrec.ac.in 的电子邮件经过验证
Kalidindi Lakshmi DivyaAssistant Professor of ECE,SRKR在 srkrec.ac.in 的电子邮件经过验证