| Carbon nanotube computer MM Shulaker, G Hills, N Patil, H Wei, HY Chen, HSP Wong, S Mitra Nature 501 (7468), 526-530, 2013 | 1169 | 2013 |
| VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using carbon nanotube FETs N Patil, A Lin, J Zhang, H Wei, K Anderson, HSP Wong, S Mitra 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 132 | 2009 |
| Carbon nanotube circuit integration up to sub-20 nm channel lengths MM Shulaker, J Van Rethy, TF Wu, L Suriyasena Liyanage, H Wei, Z Li, ... ACS nano 8 (4), 3434-3443, 2014 | 95 | 2014 |
| Robust digital VLSI using carbon nanotubes J Zhang, A Lin, N Patil, H Wei, L Wei, HS Wong, S Mitra IEEE Transactions on Computer-aided Design of integrated circuits and …, 2012 | 92 | 2012 |
| Linear increases in carbon nanotube density through multiple transfer technique MM Shulaker, H Wei, N Patil, J Provine, HY Chen, HSP Wong, S Mitra Nano letters 11 (5), 1881-1886, 2011 | 91 | 2011 |
| Monolithic 3D integration: A path from concept to reality MM Shulaker, TF Wu, MM Sabry, H Wei, HSP Wong, S Mitra 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 81 | 2015 |
| Sensor-to-digital interface built entirely with carbon nanotube FETs MM Shulaker, J Van Rethy, G Hills, H Wei, HY Chen, G Gielen, ... IEEE Journal of Solid-State Circuits 49 (1), 190-201, 2013 | 77 | 2013 |
| Scalable carbon nanotube computational and storage circuits immune to metallic and mispositioned carbon nanotubes N Patil, A Lin, J Zhang, H Wei, K Anderson, HSP Wong, S Mitra IEEE Transactions on Nanotechnology 10 (4), 744-750, 2010 | 75 | 2010 |
| Carbon nanotube robust digital VLSI J Zhang, A Lin, N Patil, H Wei, L Wei, HSP Wong, S Mitra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 68 | 2012 |
| ACCNT—A metallic-CNT-tolerant design methodology for carbon-nanotube VLSI: Concepts and experimental demonstration A Lin, N Patil, H Wei, S Mitra, HSP Wong IEEE Transactions on Electron Devices 56 (12), 2969-2978, 2009 | 54 | 2009 |
| Cooling three-dimensional integrated circuits using power delivery networks H Wei, TF Wu, D Sekar, B Cronquist, RF Pease, S Mitra 2012 International Electron Devices Meeting, 14.2. 1-14.2. 4, 2012 | 52 | 2012 |
| Carbon nanotube electronics-materials, devices, circuits, design, modeling, and performance projection HSP Wong, S Mitra, D Akinwande, C Beasley, Y Chai, HY Chen, X Chen, ... 2011 International Electron Devices Meeting, 23.1. 1-23.1. 4, 2011 | 48 | 2011 |
| Rapid co-optimization of processing and circuit design to overcome carbon nanotube variations G Hills, J Zhang, MM Shulaker, H Wei, CS Lee, A Balasingam, HSP Wong, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 44 | 2015 |
| A metallic-CNT-tolerant carbon nanotube technology using asymmetrically-correlated CNTs (ACCNT) A Lin, N Patil, H Wei, S Mitra, HSP Wong 2009 Symposium on VLSI Technology, 182-183, 2009 | 41 | 2009 |
| Monolithic three-dimensional integration of carbon nanotube FET complementary logic circuits H Wei, M Shulaker, HSP Wong, S Mitra 2013 IEEE International Electron Devices Meeting, 19.7. 1-19.7. 4, 2013 | 40 | 2013 |
| Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits H Wei, N Patil, J Zhang, A Lin, HY Chen, HSP Wong, S Mitra 2010 Symposium on VLSI Technology, 237-238, 2010 | 38 | 2010 |
| Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects H Wei, N Patil, A Lin, HSP Wong, S Mitra 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 38 | 2009 |
| ACCNT: A metallic-CNT-tolerant design methodology for carbon nanotube VLSI: Analyses and design guidelines A Lin, J Zhang, N Patil, H Wei, S Mitra, HSP Wong IEEE transactions on electron devices 57 (9), 2284-2295, 2010 | 34 | 2010 |
| Monolithic 3D integration advances and challenges: From technology to system levels MS Ebrahimi, G Hills, MM Sabry, MM Shulaker, H Wei, TF Wu, S Mitra, ... 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2014 | 28 | 2014 |
| Air-stable technique for fabricating n-type carbon nanotube FETs H Wei, HY Chen, L Liyanage, HSP Wong, S Mitra 2011 International Electron Devices Meeting, 23.2. 1-23.2. 4, 2011 | 22 | 2011 |
H.-S. Philip WongProfessor of Electrical Engineering, Stanford University在 stanford.edu 的电子邮件经过验证
