| Time efficient signed Vedic multiplier using redundant binary representation RK Barik, M Pradhan, R Panda The Journal of Engineering 2017 (3), 60-68, 2017 | 23 | 2017 |
| Efficient ASIC and FPGA implementation of cube architecture RK Barik, M Pradhan IET computers & digital techniques 11 (1), 43-49, 2017 | 19 | 2017 |
| Area-Time Efficient Square Architecture RK Barik, M Pradhan 2015-Series: Advances D 20 (1), 21-34, 2015 | 12 | 2015 |
| Efficient conversion technique from redundant binary to nonredundant binary representation RK Barik, M Pradhan, R Panda Journal of Circuits, Systems and Computers 26 (09), 1750135, 2017 | 9 | 2017 |
| Efficient hardware realization of signed arithmetic operation using IEN RK Barik, I Samal, M Pradhan 2015 IEEE Power, Communication and Information Technology Conference (PCITC …, 2015 | 6 | 2015 |
| An Efficient Redundant Binary Adder with Revised Computational Rules RK Barik, B Bhoi, M Pradhan Computers & Electrical Engineering, Elsevier 72 (11), 224-236, 2018 | 5 | 2018 |
| A modified redundant binary adder for efficient VLSI architecture E Prusty, RK Barik, M Pradhan 2016 International Conference on Advanced Communication Control and …, 2016 | 5 | 2016 |
| A low voltage and low noise CMOS RF bulk injection mixer for UWB system application S Rout, RK Barik, SK Dwibedi Int. J. Adv. Res. Electron. Commun. Eng. 3 (4), 445-452, 2014 | 2 | 2014 |
| An improved conversion circuit for redundant binary to conventional binary representation SS Tripathy, RK Barik, M Pradhan Computational Intelligence, Communications, and Business Analytics: First …, 2017 | 1 | 2017 |
| A Study on Some Unconventional Computation For High Performance VLSI Systems RK Barik http://hdl.handle.net/10603/208894, 2018 | | 2018 |
| A High-Speed Booth Multiplier Based on Redundant Binary Algorithm RK Barik, A Panda, M Pradhan Progress in Advanced Computing and Intelligent Engineering: Proceedings of …, 2018 | | 2018 |
| AN IMPROVED AND EFFICIENT MAC UNIT AND ITS IMPLEMENTATION IN FPGA RK Barik, SK Dwibedi, SS Rout, SR Sahu IJRECE 2 (2), 71-74, 2014 | | 2014 |
Rutuparna PandaECE Dept., VSS Univ of Technology, Burla在 vssut.ac.in 的电子邮件经过验证
Rutuparna PandaECE Dept., VSS Univ of Technology, Burla在 vssut.ac.in 的电子邮件经过验证
Dr. Bandan Kumar Bhoi在 vssut.ac.in 的电子邮件经过验证
Dr. Shasanka Sekhar RoutAssistant Professor在 gla.ac.in 的电子邮件经过验证