| A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error M Annoni, A Bardine, S Campanelli, P Foglia, CA Prete Computer-Aided Design 44 (6), 509-521, 2012 | 76 | 2012 |
| Analysis of static and dynamic energy consumption in nuca caches: Initial results A Bardine, P Foglia, G Gabrielli, CA Prete Proceedings of the 2007 workshop on MEmory performance: DEaling with …, 2007 | 57 | 2007 |
| A trace-driven simulator for performance evaluation of cache-based multiprocessor systems CA Prete, G Prina, L Ricciardi IEEE Transactions on Parallel and Distributed Systems 6 (9), 915-929, 1995 | 57 | 1995 |
| Graphical design of distributed applications through reusable components A Bartoli, P Corsini, G Dini, CA Prete IEEE Parallel & Distributed Technology: Systems & Applications 3 (1), 37-50, 1995 | 54 | 1995 |
| Way adaptable D-NUCA caches A Bardine, M Comparetti, P Foglia, G Gabrielli, C Prete International Journal of High Performance Systems Architecture 2 (3-4), 215-228, 2010 | 35 | 2010 |
| Leveraging data promotion for low power D-NUCA caches A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete, P Stenström 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | 35 | 2008 |
| Relating GSR signals to traditional usability metrics: Case study with an anthropomorphic web assistant P Foglia, CA Prete, M Zanda 2008 IEEE Instrumentation and Measurement Technology Conference, 1814-1818, 2008 | 29 | 2008 |
| A power-efficient migration mechanism for D-NUCA caches A Bardine, M Comparetti, P Foglia, G Gabrielli, CA Prete 2009 Design, Automation & Test in Europe Conference & Exhibition, 598-601, 2009 | 28 | 2009 |
| Trace factory: Generating workloads for trace-driven simulation of shared-bus multiprocessors R Giorgi, CA Prete, G Prina, L Ricciardi IEEE Concurrency 5 (4), 54-68, 1997 | 28 | 1997 |
| Improving power efficiency of D-NUCA caches A Bardine, P Foglia, G Gabrielli, CA Prete, P Stenström ACM SIGARCH Computer Architecture News 35 (4), 53-58, 2007 | 27 | 2007 |
| Evaluation of leakage reduction alternatives for deep submicron dynamic nonuniform cache architecture caches A Bardine, M Comparetti, P Foglia, CA Prete IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (1), 185-190, 2013 | 26 | 2013 |
| A NUCA model for embedded systems cache design P Foglia, D Mangano, CA Prete 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 41-46, 2005 | 24 | 2005 |
| The ChARM tool for tuning embedded systems CA Prete, M Graziano, F Lazzarini IEEE Micro 17 (4), 67-76, 1997 | 23 | 1997 |
| Multibug: Interative Debugging in Distributed Systems P Corsini, CA Prete IEEE Micro 6 (3), 26-33, 1986 | 23 | 1986 |
| PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors R Giorgi, CA Prete IEEE Transactions on Parallel and Distributed Systems 10 (7), 742-763, 1999 | 22 | 1999 |
| An architecture to integrate IEC 61131-3 systems in an IEC 61499 distributed solution S Campanelli, P Foglia, CA Prete Computers in Industry 72, 47-67, 2015 | 21 | 2015 |
| Web-based training on computer architecture: The case for JCachesim I Branovic, R Giorgi, A Prete Proceedings of the 2002 workshop on Computer architecture education: Held in …, 2002 | 21 | 2002 |
| RST cache memory design for a highly coupled multiprocessor system CA Prete IEEE Micro 11 (2), 16-19, 1991 | 21 | 1991 |
| Analysis of performance dependencies in NUCA-based CMP systems P Foglia, F Panicucci, CA Prete, M Solinas 2009 21st International Symposium on Computer Architecture and High …, 2009 | 20 | 2009 |
| Row‐level algorithm to improve real‐time performance of glass tube defect detection in the production phase GA De Vitis, P Foglia, CA Prete IET Image Processing 14 (12), 2911-2921, 2020 | 19 | 2020 |
