| High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding O Weber, O Faynot, F Andrieu, C Buj-Dufournet, F Allain, P Scheiblin, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 206 | 2008 |
| Engineering strained silicon on insulator wafers with the Smart CutTM technology B Ghyselen, JM Hartmann, T Ernst, C Aulnette, B Osternaud, ... Solid-state electronics 48 (8), 1285-1296, 2004 | 159 | 2004 |
| Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack V Barral, T Poiroux, F Andrieu, C Buj-Dufournet, O Faynot, T Ernst, ... 2007 IEEE International Electron Devices Meeting, 61-64, 2007 | 99 | 2007 |
| Monolithic integration of InP-based transistors on Si substrates using MBE WK Liu, D Lubyshev, JM Fastenau, Y Wu, MT Bulsara, EA Fitzgerald, ... Journal of Crystal Growth 311 (7), 1979-1983, 2009 | 73 | 2009 |
| A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates TE Kazior, JR LaRoche, D Lubyshev, JM Fastenau, WK Liu, M Urteaga, ... 2009 IEEE MTT-S International Microwave Symposium Digest, 1113-1116, 2009 | 56 | 2009 |
| Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS A Khakifirooz, K Cheng, T Nagumo, N Loubet, T Adam, A Reznicek, ... 2012 Symposium on VLSI technology (VLSIT), 117-118, 2012 | 50 | 2012 |
| Thermal oxidation of a SiGe layer and applications thereof N Daval US Patent 7,531,427, 2009 | 49 | 2009 |
| Comparative simulation analysis of process-induced variability in nanoscale SOI and bulk trigate FinFETs AR Brown, N Daval, KK Bourdelle, BY Nguyen, A Asenov IEEE Transactions on Electron Devices 60 (11), 3611-3617, 2013 | 48 | 2013 |
| Atomic implantation and thermal treatment of a semiconductor layer T Akatsu, N Daval, NP Nguyen, O Rayssac, K Bourdelle US Patent 7,449,394, 2008 | 39 | 2008 |
| Method of reducing roughness of a thick insulating layer N Daval, S Kerdiles, C Aulnette US Patent 7,446,019, 2008 | 36 | 2008 |
| New layer transfers obtained by the SmartCut process H Moriceau, F Fournel, B Aspar, B Bataillou, A Beaumont, C Morales, ... Journal of Electronic Materials 32, 829-835, 2003 | 32 | 2003 |
| Atomic scale thickness control of SOI wafers for fully depleted applications W Schwarzenbach, N Daval, V Barec, O Bonnin, PE Acosta-Alba, ... ECS Transactions 53 (5), 39, 2013 | 23 | 2013 |
| Challenges and progress in germanium-on-insulator materials and device development towards ULSI integration E Augendre, L Sanchez, L Benaissa, T Signamarcheix, JM Hartmann, ... ECS Transactions 25 (7), 351, 2009 | 23 | 2009 |
| Thermal treatment of a semiconductor layer N Daval, T Akatsu, NP Nguyen, O Rayssac, K Bourdelle US Patent App. 11/233,318, 2006 | 23 | 2006 |
| High-Performance Germanium -Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack B Liu, X Gong, G Han, PSY Lim, Y Tong, Q Zhou, Y Yang, N Daval, ... IEEE electron device letters 33 (10), 1336-1338, 2012 | 22 | 2012 |
| Methods for forming a semiconductor structure N Daval, T Akatsu, NP Nguyen, O Rayssac US Patent 7,276,428, 2007 | 22 | 2007 |
| Germanium multiple-gate field-effect transistors formed on germanium-on-insulator substrate B Liu, X Gong, C Zhan, G Han, HC Chin, ML Ling, J Li, Y Liu, J Hu, ... IEEE transactions on electron devices 60 (6), 1852-1860, 2013 | 20 | 2013 |
| Method of manufacturing a semiconductor heterostructure C Aulnette, C Figuet, N Daval US Patent 7,459,374, 2008 | 18 | 2008 |
| Treating a SiGe layer for selective etching C Delattre, N Daval US Patent App. 11/356,927, 2007 | 18 | 2007 |
| Methods for transferring a thin layer from a wafer having a buffer layer B Ghyselen, C Aulnette, B Osternaud, N Daval US Patent 6,991,956, 2006 | 18 | 2006 |
