| Low leakage CNTFET full adders RP Somineni, YP Sai, SN Leela 2015 Global Conference on Communication Technologies (GCCT), 174-179, 2015 | 13 | 2015 |
| Design of DADDA Multiplier Using High Performance and Low Power Full Adder S Nagaleela, G Shanthi, B Manisha, P Bharath, E Praneeth 2023 14th International Conference on Computing Communication and Networking …, 2023 | 4 | 2023 |
| Design of Wallace tree multiplier circuit using high performance and low power full adder SN Leela, B Manisha, P Bharath, E Praneeth E3S Web of Conferences 391, 01025, 2023 | 4 | 2023 |
| Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology G Shanthi, G Sainath, N Ashwini, PG Sai, PA Kumar, SN Leela 2024 5th International Conference for Emerging Technology (INCET), 1-6, 2024 | 1 | 2024 |
| A Novel Design of High Speed Multiplier Using Hybrid Adder Technique SN Leela, DK Chandrika, K Swetha, DG Kalali, G Shanthi 2024 3rd International Conference for Innovation in Technology (INOCON), 1-5, 2024 | 1 | 2024 |
| Design of Shift Registers Using DG-FinFET for Low Power Applications G Shanthi, KN Vaishnavi, N Manasa, VS Pramod, SN Leela, SS Vali 2024 7th International Conference on Devices, Circuits and Systems (ICDCS …, 2024 | | 2024 |
