| The energy efficiency of IRAM architectures R Fromm, S Perissakis, N Cardwell, C Kozyrakis, B McGaughy, ... ACM SIGARCH Computer Architecture News 25 (2), 327-337, 1997 | 155 | 1997 |
| An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique JC Chen, BW McGaughy, D Sylvester, C Hu International Electron Devices Meeting. Technical Digest, 69-72, 1996 | 154 | 1996 |
| Design tools for reliability analysis Z Liu, BW McGaughy, JZ Ma Proceedings of the 43rd annual Design Automation Conference, 182-187, 2006 | 65 | 2006 |
| Second-Order Balanced Truncation for Passive-Order Reduction of RLCK Circuits B Yan, SXD Tan, B McGaughy IEEE Transactions on Circuits and Systems II: Express Briefs 55 (9), 942-946, 2008 | 50 | 2008 |
| System and method for simulating a circuit having hierarchical structure BW McGaughy, P Karhade, J Muhkerjee, J Kong US Patent 7,181,383, 2007 | 49 | 2007 |
| An efficient method for terminal reduction of interconnect circuits considering delay variations P Liu, SXD Tan, H Li, Z Qi, J Kong, B McGaughy, L He ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 49 | 2005 |
| A simple method for on-chip, sub-femto farad interconnect capacitance measurement BW McGaughy, JC Chen, D Sylvester, C Hu IEEE Electron device letters 18 (1), 21-23, 1997 | 41 | 1997 |
| An efficient terminal and model order reduction algorithm P Liu, SXD Tan, B Yan, B McGaughy Integration 41 (2), 210-218, 2008 | 36 | 2008 |
| ETBR: Extended truncated balanced realization method for on-chip power grid network analysis D Li, SXD Tan, B McGaughy Proceedings of the conference on Design, automation and test in Europe, 432-437, 2008 | 34 | 2008 |
| Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure BW Mcgaughy US Patent 7,257,525, 2007 | 32 | 2007 |
| Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure BW Mcgaughy US Patent 7,415,403, 2008 | 27 | 2008 |
| Method and system for validating a hierarchical simulation database BW Mcgaughy, J Kong US Patent 7,434,183, 2008 | 26 | 2008 |
| Termmerg: an efficient terminal-reduction method for interconnect circuits P Liu, SXD Tan, B McGaughy, L Wu, L He IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 26 | 2007 |
| System and method for adaptive partitioning of circuit components during simulation BW McGaughy, P Frey, J Kong, B Yang US Patent 7,024,652, 2006 | 26 | 2006 |
| Hot carrier circuit reliability simulation L Wu, Z Liu, AI Chen, JY Choi, BW Mcgaughy US Patent 7,292,968, 2007 | 25 | 2007 |
| Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure BW McGaughy, P Karhade, P Wan, M Singh US Patent 7,143,021, 2006 | 25 | 2006 |
| Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure BW Mcgaughy US Patent 7,328,143, 2008 | 24 | 2008 |
| SBPOR: second-order balanced truncation for passive order reduction of RLC circuits B Yan, SXD Tan, P Liu, B McGaughy Proceedings of the 44th annual Design Automation Conference, 158-161, 2007 | 24 | 2007 |
| System and method for converting a flat netlist into a hierarchical netlist BW Mcgaughy, P Frey, B Krichevskiy US Patent 7,272,805, 2007 | 23 | 2007 |
| An extended SVD-based terminal and model order reduction algorithm P Liu, S X-d Tan, B Yan, B McGaughy 2006 IEEE International Behavioral Modeling and Simulation Workshop, 44-49, 2006 | 22 | 2006 |
