Memristor based computation-in-memory architecture for data-intensive applications S Hamdioui, L Xie, HA Du Nguyen, M Taouil, K Bertels, H Corporaal, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 234 | 2015 |
Scouting logic: A novel memristor-based logic design for resistive computing L Xie, HA Du Nguyen, J Yu, A Kaichouhi, M Taouil, M AlFailakawi, ... 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 176-181, 2017 | 125 | 2017 |
Fast boolean logic mapped on memristor crossbar L Xie, HA Du Nguyen, M Taouil, S Hamdioui, K Bertels 2015 33rd IEEE International Conference on Computer Design (ICCD), 335-342, 2015 | 117 | 2015 |
Testing open defects in memristor-based memories S Hamdioui, M Taouil, NZ Haron IEEE Transactions on Computers 64 (1), 247-259, 2013 | 115 | 2013 |
Test cost analysis for 3D die-to-wafer stacking M Taouil, S Hamdioui, K Beenakker, EJ Marinissen 2010 19th IEEE Asian Test Symposium, 435-441, 2010 | 67 | 2010 |
Memristive devices for computation-in-memory J Yu, HA Du Nguyen, L Xie, M Taouil, S Hamdioui 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 64 | 2018 |
A classification of memory-centric computing HAD Nguyen, J Yu, MA Lebdeh, M Taouil, S Hamdioui, F Catthoor ACM Journal on Emerging Technologies in Computing Systems (JETC) 16 (2), 1-26, 2020 | 59 | 2020 |
On maximizing the compound yield for 3D wafer-to-wafer stacked ICs M Taouil, S Hamdioui, J Verbree, EJ Marinissen 2010 IEEE International Test Conference, 1-10, 2010 | 57 | 2010 |
Device-aware test: A new test approach towards DPPB level M Fieback, L Wu, GC Medeiros, H Aziza, S Rao, EJ Marinissen, M Taouil, ... 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 56 | 2019 |
Memristive devices for computing: Beyond CMOS and beyond von Neumann HA Du Nguyen, J Yu, L Xie, M Taouil, S Hamdioui, D Fey 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017 | 51 | 2017 |
Challenges and solutions in emerging memory testing EI Vatajelu, P Prinetto, M Taouil, S Hamdioui IEEE Transactions on Emerging Topics in Computing 7 (3), 493-506, 2017 | 51 | 2017 |
Electrical modeling of STT-MRAM defects L Wu, M Taouil, S Rao, EJ Marinissen, S Hamdioui 2018 IEEE International Test Conference (ITC), 1-10, 2018 | 43 | 2018 |
A mapping methodology of boolean logic circuits on memristor crossbar L Xie, HA Du Nguyen, M Taouil, S Hamdioui, K Bertels IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 43 | 2017 |
Applications of computation-in-memory architectures based on memristive devices S Hamdioui, HA Du Nguyen, M Taouil, A Sebastian, M Le Gallo, S Pande, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 486-491, 2019 | 41 | 2019 |
Integral impact of BTI, PVT variation, and workload on SRAM sense amplifier I Agbo, M Taouil, D Kraak, S Hamdioui, H Kükner, P Weckx, P Raghavan, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2017 | 41 | 2017 |
On the implementation of computation-in-memory parallel adder HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 39 | 2017 |
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface EJ Marinissen, B De Wachter, K Smith, J Kiesewetter, M Taouil, ... 2014 International Test Conference, 1-10, 2014 | 37 | 2014 |
Parallel matrix multiplication on memristor-based computation-in-memory architecture A Haron, J Yu, R Nane, M Taouil, S Hamdioui, K Bertels 2016 International Conference on High Performance Computing & Simulation …, 2016 | 33 | 2016 |
Layer redundancy based yield improvement for 3D wafer-to-wafer stacked memories M Taouil, S Hamdioui 2011 Sixteenth IEEE European Test Symposium, 45-50, 2011 | 32 | 2011 |
Computation-in-memory based parallel adder HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015 | 30 | 2015 |