| Constructive Analysis of Cyclic Circuits TR Shiple, G Berry, H Touati Proceedings European Design and Test Conference, 328-333, 1996 | 213 | 1996 |
| Smart simulation using collaborative formal and simulation engines PH Ho, T Shiple, K Harer, J Kukula, R Damiano, V Bertacco, J Taylor, ... IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000 | 173 | 2000 |
| Heuristic minimization of BDDs using don't cares TR Shiple, R Hojati, AL Sangiovanni-Vincentelli, RK Brayton Proceedings of the 31st annual Design Automation Conference, 225-231, 1994 | 150 | 1994 |
| HSIS: A BDD-based environment for formal verification A Aziz, F Balarin, ST Cheng, R Hojati, T Kam, SC Krishnan, RK Ranjan, ... Proceedings of the 31st annual Design Automation Conference, 454-459, 1994 | 107 | 1994 |
| Approximation and decomposition of binary decision diagrams K Ravi, KL McMillan, TR Shiple, F Somenzi Proceedings of the 35th annual Design Automation Conference, 445-450, 1998 | 105* | 1998 |
| Formal analysis of synchronous circuits TR Shiple University of California, Berkeley, 1996 | 81 | 1996 |
| A Comparison of Presburger Engines for EFSM Reachability TR Shiple, JH Kukula, RK Ranjan International Conference on Computer Aided Verification, 280-292, 1998 | 80 | 1998 |
| Building circuits from relations JH Kukula, TR Shiple Computer Aided Verification: 12th International Conference, CAV 2000 …, 2000 | 65 | 2000 |
| Formula-dependent equivalence for compositional CTL model checking A Aziz, TR Shiple, V Singhal, AL Sangiovanni-Vincentelli Computer Aided Verification: 6th International Conference, CAV'94 Stanford …, 1994 | 56 | 1994 |
| Constructive Boolean circuits and the exactness of timed ternary simulation M Mendler, TR Shiple, G Berry Formal Methods in System Design 40, 283-329, 2012 | 50 | 2012 |
| VIS RK Brayton, GD Hachtel, A Sangiovanni-Vincentelli, F Somenzi, A Aziz, ... International Conference on Formal Methods in Computer-Aided Design, 248-256, 1996 | 50 | 1996 |
| Analysis of combinational cycles in sequential circuits TR Shiple, V Singhal, RK Brayton, AL Sangiovnni-Vincentelli 1996 IEEE International Symposium on Circuits and Systems (ISCAS) 4, 592-595, 1996 | 34 | 1996 |
| A unified approach to language containment and fair CTL model checking R Hojati, TR Shiple, RK Brayton, RP Kurshan Proceedings of the 30th international Design Automation Conference, 475-481, 1993 | 30 | 1993 |
| Automatic compositional minimization in CTL model checking M Chiodo, TR Shiple, AL Sangiovanni-Vincentelli, RK Brayton IEEE INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, 172-172, 1992 | 30 | 1992 |
| VIS User’s Manual T Villa, G Swamy, T Shiple, A Aziz, R Brayton, S Edwards, G Hachtel, ... Electronics Research Laboratory, University of Colorado at Boulder, 1996 | 24 | 1996 |
| Formula-dependent equivalence for compositional CTL model checking A Aziz, T Shiple, V Singhal, R Brayton, A Sangiovanni-Vincentelli Formal Methods in System Design 21, 193-224, 2002 | 21 | 2002 |
| Simplifying circuits for formal verification using parametric representation IH Moon, HH Kwak, J Kukula, T Shiple, C Pixley Formal Methods in Computer-Aided Design: 4th International Conference, FMCAD …, 2002 | 20 | 2002 |
| Method and system for automata-based approach to state reachability of interacting extended finite state machines JH Kukula, TR Shiple US Patent 6,059,837, 2000 | 20 | 2000 |
| Combinational equivalence checking through function transformation HH Kwak, IH Moon, JH Kukula, TR Shiple Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 13 | 2002 |
| Method and apparatus for formally constraining random simulation JH Kukula, TR Shiple, RK Ranjan US Patent 7,092,858, 2006 | 8 | 2006 |
Alberto Sangiovanni VincentelliProfessor of EECS, University of California, Berkeley在 eecs.berkeley.edu 的电子邮件经过验证
