| A 16-channel low-power nonuniform spaced filter bank core for digital hearing aids KS Chong, BH Gwee, JS Chang IEEE Transactions on Circuits and Systems II: Express Briefs 53 (9), 853-857, 2006 | 90 | 2006 |
| A micropower low-voltage multiplier with reduced spurious switching KS Chong, BH Gwee, JS Chang IEEE transactions on very large scale integration (VLSI) systems 13 (2), 255-265, 2005 | 79 | 2005 |
| Microstrip series fed antenna array for millimeter wave automotive radar applications YI Chong, DOU Wenbin 2012 IEEE MTT-S International Microwave Workshop Series on Millimeter Wave …, 2012 | 68 | 2012 |
| Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors KS Chong, BH Gwee, JS Chang IEEE journal of solid-state circuits 42 (9), 2034-2045, 2007 | 64 | 2007 |
| Synchronous-logic and asynchronous-logic 8051 microcontroller cores for realizing the internet of things: A comparative study on dynamic voltage scaling and variation effects KL Chang, JS Chang, BH Gwee, KS Chong IEEE journal on emerging and selected topics in circuits and systems 3 (1 …, 2013 | 62 | 2013 |
| An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive System for Wireless Sensor Networks T Lin, KS Chong, JS Chang, BH Gwee IEEE Journal of Solid-State Circuits 48 (2), 573-586, 2012 | 56 | 2012 |
| Interceptive side channel attack on AES-128 wireless communications for IoT applications AA Pammu, KS Chong, WG Ho, BH Gwee 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 650-653, 2016 | 52 | 2016 |
| Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors KS Chong, KL Chang, BH Gwee, JS Chang IEEE Journal of Solid-state circuits 47 (3), 769-780, 2012 | 46 | 2012 |
| Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic T Lin, KS Chong, BH Gwee, JS Chang 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 3162-3165, 2009 | 46 | 2009 |
| A high throughput and secure authentication-encryption AES-CCM algorithm on asynchronous multicore processor AA Pammu, WG Ho, NKZ Lwin, KS Chong, BH Gwee IEEE Transactions on Information Forensics and Security 14 (4), 1023-1036, 2018 | 38 | 2018 |
| A low-voltage micropower asynchronous multiplier with shift–add multiplication approach BH Gwee, JS Chang, Y Shi, CC Chua, KS Chong IEEE Transactions on Circuits and Systems I: Regular Papers 56 (7), 1349-1359, 2008 | 30 | 2008 |
| High secured low power multiplexer-LUT based AES S-box implementation AA Pammu, KS Chong, KZL Ne, BH Gwee 2016 International Conference on Information Systems Engineering (ICISE), 3-7, 2016 | 28 | 2016 |
| Sense amplifier half-buffer (SAHB) a low-power high-performance asynchronous logic QDI cell template KS Chong, WG Ho, T Lin, BH Gwee, JS Chang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 402-415, 2016 | 24 | 2016 |
| Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES: Design, countermeasures and evaluation KS Chong, JS Ng, J Chen, NKZ Lwin, NA Kyaw, WG Ho, J Chang, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11 (2 …, 2021 | 23 | 2021 |
| Counteracting differential power analysis: Hiding encrypted data from circuit cells KS Chong, KZL Ne, WG Ho, N Liu, AH Akbar, BH Gwee, JS Chang 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | 22 | 2015 |
| Quasi-delay-insensitive compiler: Automatic synthesis of asynchronous circuits from verilog specifications R Zhou, KS Chong, BH Gwee, JS Chang 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 22 | 2011 |
| Low energy 16-bit Booth leapfrog array multiplier using dynamic adders KS Chong, BH Gwee, JS Chang IET circuits, devices & systems 1 (2), 170-174, 2007 | 21 | 2007 |
| Low gate-count ultra-small area nano advanced encryption standard (AES) design A Shreedhar, KS Chong, NKZ Lwin, NA Kyaw, L Nalangilli, W Shu, ... 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 18 | 2019 |
| Asynchronous-Logic QDI quad-rail sense-amplifier half-buffer approach for NoC router design WG Ho, KS Chong, KZL Ne, BH Gwee, JS Chang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 196-200, 2017 | 18 | 2017 |
| Analytical delay variation modeling for evaluating sub-threshold synchronous/asynchronous designs T Lin, KS Chong, BH Gwee, JS Chang, ZX Qiu Proceedings of the 8th IEEE International NEWCAS Conference 2010, 69-72, 2010 | 17 | 2010 |
