| FastGR: Global Routing on CPU–GPU With Heterogeneous Task Graph Scheduler S Liu, Y Pu, P Liao, H Wu, R Zhang, Z Chen, W Lv, Y Lin, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 24 | 2022 |
| Restructure-tolerant timing prediction via multimodal fusion Z Wang, S Liu, Y Pu, S Chen, TY Ho, B Yu 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 10 | 2023 |
| Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA Y Pu, Z He, T Qiu, H Wu, B Yu arXiv preprint arXiv:2407.15353, 2024 | 1 | 2024 |
| Neuroselect: Learning to select clauses in sat solvers H Liu, P Xu, Y Pu, L Yin, HL Zhen, M Yuan, TY Ho, B Yu ACM/IEEE Design Automation Conference (DAC), 2024 | 1 | 2024 |
| ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling Z Wang, W Zhao, Y Pu, L Chen, WWK Thong, W Sheng, TY Ho, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells Y Zhang, Y Pu, F Liu, P Liao, KY Chao, K Zhu, Y Lin, B Yu Proceedings of the 2024 International Symposium on Physical Design, 161-168, 2024 | | 2024 |
| IncreMacro: Incremental Macro Placement Refinement Y Pu, T Chen, Z He, C Bai, H Zheng, Y Lin, B Yu Proceedings of the 2024 International Symposium on Physical Design, 169-176, 2024 | | 2024 |
| Lesyn: Placement-Aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs Y Pu, F Liu, Y Zhang, Z He, Y Lin, KY Chao, B Yu | | 2024 |
