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Yifan Yang
Yifan Yang
Nvidia
在 csail.mit.edu 的电子邮件经过验证 - 首页
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Synetgy: Algorithm-hardware co-design for convnet accelerators on embedded fpgas
Y Yang, Q Huang, B Wu, T Zhang, L Ma, G Gambardella, M Blott, ...
Proceedings of the 2019 ACM/SIGDA international symposium on field …, 2019
1482019
GraphABCD: Scaling out graph analytics with asynchronous block coordinate descent
Y Yang, Z Li, Y Deng, Z Liu, S Yin, S Wei, L Liu
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
292020
SpZip: Architectural support for effective data compression in irregular applications
Y Yang, JS Emer, D Sanchez
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
262021
ISOSceles: Accelerating sparse CNNs through inter-layer pipelining
Y Yang, JS Emer, D Sanchez
2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023
202023
Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications
Y Yang, JS Emer, D Sanchez
2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture …, 2024
12024
Azul: An Accelerator for Sparse Iterative Solvers Leveraging Distributed On-Chip Memory
A Feldmann, C Golden, Y Yang, JS Emer, D Sanchez
2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 643-656, 2024
2024
Architectural Support for Effective Data Compression In Irregular Applications
Y Yang
Massachusetts Institute of Technology, 2021
2021
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