Synetgy: Algorithm-hardware co-design for convnet accelerators on embedded fpgas Y Yang, Q Huang, B Wu, T Zhang, L Ma, G Gambardella, M Blott, ... Proceedings of the 2019 ACM/SIGDA international symposium on field …, 2019 | 148 | 2019 |
GraphABCD: Scaling out graph analytics with asynchronous block coordinate descent Y Yang, Z Li, Y Deng, Z Liu, S Yin, S Wei, L Liu 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 29 | 2020 |
SpZip: Architectural support for effective data compression in irregular applications Y Yang, JS Emer, D Sanchez 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 26 | 2021 |
ISOSceles: Accelerating sparse CNNs through inter-layer pipelining Y Yang, JS Emer, D Sanchez 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 20 | 2023 |
Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications Y Yang, JS Emer, D Sanchez 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture …, 2024 | 1 | 2024 |
Azul: An Accelerator for Sparse Iterative Solvers Leveraging Distributed On-Chip Memory A Feldmann, C Golden, Y Yang, JS Emer, D Sanchez 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 643-656, 2024 | | 2024 |
Architectural Support for Effective Data Compression In Irregular Applications Y Yang Massachusetts Institute of Technology, 2021 | | 2021 |